Automatic design of low-power encoders using reversible circuit synthesis

The application of coding strategies is an established methodology to improve the characteristics of on-chip interconnect architectures. Therefore, design methods are required which realize the corresponding encoders and decoders with as small as possible overhead in terms of power and delay. In the past, conventional design methods have been applied for this purpose.

[1]  Naresh R. Shanbhag,et al.  Coding for systern-on-chip networks: a unified framework , 2004, Proceedings. 41st Design Automation Conference, 2004..

[2]  Pérès,et al.  Reversible logic and quantum computers. , 1985, Physical review. A, General physics.

[3]  Leandro Soares Indrusiak,et al.  Low-Power Coding for Networks-on-Chip with Virtual Channels , 2009, J. Low Power Electron..

[4]  Luca Benini,et al.  Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Nikil Dutt,et al.  On-Chip Communication Architectures: System on Chip Interconnect , 2008 .

[6]  David Blaauw,et al.  A robust edge encoding technique for energy-efficient multi-cycle interconnect , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[7]  Stefan Frehse,et al.  RevKit: A Toolkit for Reversible Circuit Design , 2012, J. Multiple Valued Log. Soft Comput..

[8]  Gerhard W. Dueck,et al.  A transformation based algorithm for reversible logic synthesis , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  Niraj K. Jha,et al.  An Algorithm for Synthesis of Reversible Logic Circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Robert Wille,et al.  SyReC: A Programming Language for Synthesis of Reversible Circuits , 2010, FDL.

[11]  Robert Wille,et al.  Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Luca Benini,et al.  Architectures and synthesis algorithms for power-efficient businterfaces , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  T. Toffoli,et al.  Conservative logic , 2002, Collision-Based Computing.

[14]  Alberto García Ortiz,et al.  On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects , 2007, PATMOS.

[15]  Naresh R. Shanbhag,et al.  A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Robert Wille,et al.  BDD-based synthesis of reversible logic for large functions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[17]  Partha Pratim Pande,et al.  Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Gerhard W. Dueck,et al.  Techniques for the synthesis of reversible Toffoli networks , 2006, TODE.

[19]  John P. Hayes,et al.  Synthesis of reversible logic circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Thierry Paul,et al.  Quantum computation and quantum information , 2007, Mathematical Structures in Computer Science.

[21]  Tommaso Toffoli,et al.  Reversible Computing , 1980, ICALP.

[22]  Robert Wille,et al.  Towards a Design Flow for Reversible Logic , 2010 .