论文信息 - Synthesis of orthogonal systolic arrays for fault-tolerant matrix multiplication

Synthesis of orthogonal systolic arrays for fault-tolerant matrix multiplication

This paper presents a procedure for designing fault-tolerant systolic array with orthogonal interconnects and bidirectional data flow (2DBOSA) for matrix multiplication. The method employs space-time redundancy to achieve fault-tolerance. The obtained array has Ω = n(n+2) processing elements, and total execution time of Ttot = 6n -5. The array can tolerate single transient errors and the majority of multiple error patterns with high probability. Compared to hexagonal array of same dimensions, the number of I/O pins is reduced for approximately 30%.

M K Stojčev | E I Milovanović | S R Marković | I Ž Milovanović

[1] Maurice Tchuente,et al. Complexity of Matrix Product on a Class of Orthogonally Connected Systolic Arrays , 1987, IEEE Transactions on Computers.

[2] Asim J. Al-Khalili,et al. Fault-tolerant design methodology for systolic array architectures , 1994 .

[3] C. N. Zhang. Systematic design of systolic arrays for computing multiple problem instances , 1992 .

[4] Mile K. Stojcev,et al. Hexagonal systolic arrays for matrix multiplication , 2001 .

[5] S. Kung,et al. VLSI Array processors , 1985, IEEE ASSP Magazine.

[6] Chein-Wei Jen,et al. Redundancy design for a fault tolerant systolic array , 1990 .

[7] David J. Evans,et al. Nineteen ways of systolic matrix multiplication , 1998, Int. J. Comput. Math..

[8] N. M. Stojanovi,et al. Mapping matrix multiplication algorithm onto fault-tolerant systolic array , 2004 .

[9] Emina I. Milovanovic,et al. The Design of Optimal Planar Systolic Arrays for Matrix Multiplication , 1997 .

[10] C. R. Wan,et al. Massive parallel processing for matrix multiplication: a systolic approach , 2001 .

[11] Stanislav G. Sedukhin. Design and analysis of systolic algorithms and structures , 1992 .

[12] C. N. Zhang,et al. Optimal fault-tolerant design approach for VLSI array processors , 1997 .