OBDD Minimization Based on Two-Level Representation of Boolean Functions
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[1] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD 1993.
[2] Sheldon B. Akers,et al. Binary Decision Diagrams , 1978, IEEE Transactions on Computers.
[3] Albert R. Wang,et al. Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[4] Hiroshi Sawada,et al. Minimization of binary decision diagrams based on exchanges of variables , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[5] 藤田 昌宏,et al. Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams , 1988 .
[6] Don E. Ross,et al. Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams , 1991, 28th ACM/IEEE Design Automation Conference.
[7] Malgorzata Marek-Sadowska,et al. On designing universal logic blocks and their application to FPGA design , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Chikahiro Hori,et al. Interleaving based variable ordering methods for ordered binary decision diagrams , 1993, ICCAD.
[9] Richard Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.
[10] Yuke Wang,et al. Solving Boolean Equations Using ROSOP Forms , 1998, IEEE Trans. Computers.
[11] E BryantRandal. Graph-Based Algorithms for Boolean Function Manipulation , 1986 .
[12] Martin D. F. Wong,et al. Series-parallel functions and FPGA logic module design , 1996, TODE.
[13] Kenneth J. Supowit,et al. Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1990, IEEE Trans. Computers.
[14] Masahiro Fujita,et al. Evaluation and improvement of Boolean comparison method based on binary decision diagrams , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[15] Rolf Drechsler,et al. On Variable Ordering and Decomposition Type Choice in OKFDDs , 1998, IEEE Trans. Computers.
[16] P. R. Stephan,et al. SIS : A System for Sequential Circuit Synthesis , 1992 .
[17] Randal E. Bryant,et al. On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.
[18] Yu-Liang Wu,et al. Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[19] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[20] Kenneth J. Supowit,et al. Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1987, 24th ACM/IEEE Design Automation Conference.
[21] Masahiro Fujita,et al. On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..
[22] Fabio Somenzi,et al. Logic synthesis and verification algorithms , 1996 .
[23] Nagisa Ishiura,et al. Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.
[24] CoudertOlivier. Two-level logic minimization: an overview , 1994 .
[25] Mostafa H. Abd-El-Barr,et al. An Algorithm for Total Symmetric OBDD Detection , 1997, IEEE Trans. Computers.
[26] M. R. Mercer,et al. Fast functional evaluation of candidate OBDD variable orderings , 1991, Proceedings of the European Conference on Design Automation..
[27] Rolf Drechsler,et al. Fast exact minimization of BDDs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[28] Olivier Coudert,et al. Two-level logic minimization: an overview , 1994, Integr..
[29] Jacob A. Abraham,et al. Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions , 1997, IEEE Trans. Computers.
[30] Fabio Somenzi,et al. Variable ordering for binary decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.
[31] Hiroshige Fujii,et al. Interleaving based variable ordering methods for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[32] Martin D. F. Wong,et al. Universal Logic Modules for Series-Parallel Functions , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.