A 1.2GS/s 15b DAC for precision signal generation

A 1.2GS/s 15b DAC achieves untrimmed SFDR of -70dBc to f/sub s//4 and -63dBc to Nyquist (with 10dB better results at 500MS/s). A per-element resampling scheme and dynamic element matching achieve DNL of 2LSB. In RZ output mode, ACPR for a 20MHz band at 900MHz is 69dB. The chip uses 40GHz-f/sub T/ NPN and is implemented in 0.35 /spl mu/m CMOS.

[1]  R. Adams,et al.  A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[2]  J.D.H. Alexander.  Clock recovery from random binary signals , 1975 .