A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

This paper describes a 2.2 ns search-time, 0.7 fJ/bit/search 0.1 /spl mu/m CMOS TCAM which uses NOR cells for high-speed coarse search and NAND cells for low-power fine search. A hidden bank selection eliminates the timing penalty for partial activation, a match line repeater enhances the search speed and column decoding enables high memory density.