Budget Management with Applications

AbstractGiven a directed acyclic graph with timing constraints, the budget management problem is to assign to each vertex an incremental delay such that the sum of these delays is maximized without violating given constraints. We propose the notion of slack sensitivity and budget gradient to demonstrate the characteristics of budget management. We develop a polynomial-time algorithm for the budget management problem, based on the maximum independent set of an established transitive graph . We show the comparison of our approach with the well-known zero-slack algorithm , and extend it to general weighted graphs . Applications to a class of problems in VLSI CAD are also discussed.

[1]  C. L. Liu,et al.  A new performance driven placement algorithm , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[2]  Majid Sarrafzadeh,et al.  An effective algorithm for gate-level power-delay tradeoff using two voltages , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[3]  Habib Youssef,et al.  Timing constraints for correct performance , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[4]  Ankur Srivastava,et al.  On gate level power optimization using dual-supply voltages , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[5]  How-Rern Lin,et al.  Power reduction by gate sizing with path-oriented slack calculation , 1995, ASP-DAC '95.

[6]  R. Möhring Algorithmic Aspects of Comparability Graphs and Interval Graphs , 1985 .

[7]  Martin D. F. Wong,et al.  Closed form solution to simultaneous buffer insertion/sizing and wire sizing , 1997, ISPD '97.

[8]  Patrick Girard,et al.  A gate resizing technique for high reduction in power consumption , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[9]  Carl Sechen,et al.  Timing Driven Placement for Large Standard Cell Circuits , 1995, 32nd Design Automation Conference.

[10]  Ravi Nair,et al.  Generation of performance constraints for layout , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  S. Tragoudas,et al.  Maximum independent sets on transitive graphs and their applications in testing and CAD , 1997, ICCAD 1997.