ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding

This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory and communication interconnect scheme. This application-specific instruction-set processor has an SIMD architecture with a specialized and extensible instruction-set and 5-stages pipeline control. The attached memories and communication interfaces enable the design of efficient multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffling technique introduced in the turbo-decoding field to reduce communication latency. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for various standards and operating modes. Results obtained for double binary DVB-RCS turbo codes demonstrate a 100 Mbit/s throughput using 16-ASIP multiprocessor architecture

[1]  D.J.C. MacKay,et al.  Good error-correcting codes based on very sparse matrices , 1997, Proceedings of IEEE International Symposium on Information Theory.

[2]  Norbert Wehn,et al.  A Scalable System Architecture for High-Throughput Turbo-Decoders , 2005, J. VLSI Signal Process..

[3]  Patrick Robertson,et al.  Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding , 1997, Eur. Trans. Telecommun..

[4]  A. Mullin,et al.  Mathematical Theory of Connecting Networks and Telephone Traffic. , 1966 .

[5]  Keshab K. Parhi,et al.  Parallel Turbo decoding , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[6]  Vincent C. Gaudet,et al.  On multiple slice turbo codes , 2005, Ann. des Télécommunications.

[7]  V. Benes,et al.  Mathematical Theory of Connecting Networks and Telephone Traffic. , 1966 .

[8]  John Cocke,et al.  Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.

[9]  Heinrich Meyr,et al.  A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[10]  Zhou Liang,et al.  A low complex parallel decoding structure for turbo-codes , 2000, WCC 2000 - ICCT 2000. 2000 International Conference on Communication Technology Proceedings (Cat. No.00EX420).

[11]  Michel Jezequel,et al.  The Turbo Code Standard for DVB-RCS , 2004 .

[12]  Alex Orailoglu,et al.  Application-specific microprocessors , 2003 .

[13]  Alexander V. Veidenbaum,et al.  Guest Editors' Introduction: Application-Specific Microprocessors , 2003, IEEE Des. Test Comput..

[14]  Luciano Lavagno,et al.  Implementation of a UMTS turbo-decoder on a dynamically reconfigurable platform , 2004 .

[15]  Norbert Wehn,et al.  Communication centric architectures for turbo-decoding on embedded multiprocessors , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[16]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[17]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[18]  Marc P. C. Fossorier,et al.  Shuffled iterative decoding , 2005, IEEE Transactions on Communications.