Design for Autonomous Test

A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible.

[1]  D. C. King Diagnosis and reliable design of digital systems , 1977 .

[2]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[3]  Huiyan Wang,et al.  The ttl data book for design engineers , 1981 .

[4]  Thomas W. Williams,et al.  Testing Logic Networks and Designing for Testability , 1979, Computer.

[5]  James E. Smith,et al.  Measures of the Effectiveness of Fault Signature Analysis , 1980, IEEE Transactions on Computers.

[6]  Jack Edward Stephenson,et al.  A testability measure for register-transfer level digital circuits , 1974 .

[7]  Edward J. McCluskey Verification Testing , 1982, 19th Design Automation Conference.

[8]  Peter S. Bottorff,et al.  Test generation for large logic networks , 1977, DAC '77.

[9]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[10]  Jacob Savir,et al.  Syndrome-Testable Design of Combinational Circuits , 1980, IEEE Transactions on Computers.

[11]  J. Mucha,et al.  Built-In Test for Complex Digital Integrated Circuits , 1979, Fifth European Solid State Circuits Conference - ESSCIRC 79.

[12]  John E. Bauer,et al.  An Advanced Fault Isolation System for Digital Logic , 1975, IEEE Transactions on Computers.

[13]  Edward J. McCluskey,et al.  Design for autonomous test , 1981 .

[14]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[15]  B. Koenemann,et al.  Built-in logic block observation techniques , 1979 .

[16]  Edward J. McCluskey,et al.  Design of Digital Computers , 1975, Texts and Monographs in Computer Science.