A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications

Satellite communication plays a vital role in extending 5G cellular networks to hard-to-reach areas, including airplanes, railways, shipments, other transport mechanisms, and especially in rural regions of the country that are traditionally beyond the reach of cellular service providers. The devices, specifically those incorporating static memories, being employed for satellite communication, face the challenge of getting prone to cosmic radiations or alpha particle strikes. These strikes cause multi-bit errors in static-memory cells that lead to loss of total output yield. This work proposes a low power twelve transistor (12T) SRAM cell that confirms a reduction in multi-bit errors for the Internet of things based devices supporting fifth-generation (5G) communication system. The proposed SRAM ensures improved read and write ability by utilizing a read decoupled access path and loop cutting mechanism, respectively. The proposed design improves read/write stability by 2.02  $$\times$$ /1.05 $$\,\times$$ in comparison to conventional 6T cell with 2.52  $$\times$$  silicon space overhead. The area overhead is neutralized by 3.17 $$\times$$ improvement in $$I_{on}$$ / $$I_{off}$$ ratio that improves cell density of SRAM cell. The improved critical charge of the proposed 12T SRAM cell is compared with four other considered cells to ensure the reduction in multi-bit soft errors, and thereby confirming its suitability for devices supporting satellite communications. The proposed design successfully eliminates the half-select issue that enables the implementation of the bit-interleaved architecture. The leakage power of the proposed 12T cell is improved by 2.65 $$\times$$ in comparison to conventional 6T attributed to series-connected devices used as loop cutting pair. This reduction of leakage power remains sustained till 110 $$^{\circ }$$ temperature. The simulation of this work has been conducted with cadence virtuoso tool using GPDK 45 nm technology file.

[1]  Gerhard P. Hancke,et al.  A Survey on 5G Networks for the Internet of Things: Communication Technologies and Challenges , 2018, IEEE Access.

[2]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[3]  Jongsun Park,et al.  Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Mohd. Hasan,et al.  A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell , 2012, Microelectron. Reliab..

[5]  P. E. Dodd,et al.  Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.

[6]  Ashish Sachdeva,et al.  A Schmitt-trigger based low read power 12T SRAM cell , 2020, Analog Integrated Circuits and Signal Processing.

[7]  Massimo Alioto,et al.  Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Chien-Yu Lu,et al.  A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing , 2012, IEEE Journal of Solid-State Circuits.

[9]  Sied Mehdi Fakhraie,et al.  A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  C. B. Kushwah,et al.  A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Yong Li,et al.  Differential-read 8T SRAM cell with tunable access and pull-down transistors , 2012 .

[12]  Ming-Hsien Tu,et al.  40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Santosh Kumar Vishvakarma,et al.  An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network , 2019, Microelectron. J..

[14]  Sudeb Dasgupta,et al.  Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes , 2018, IEEE Transactions on Semiconductor Manufacturing.

[15]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[16]  Meng-Fan Chang,et al.  A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications , 2009, IEEE Journal of Solid-State Circuits.

[17]  Volkan Kursun,et al.  Low power and robust memory circuits with asymmetrical ground gating , 2016, Microelectron. J..

[18]  Santosh Kumar Vishvakarma,et al.  Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications , 2020, J. Electron. Test..

[19]  Vinay Tomar,et al.  Design of a Stable Low Power 11-T Static Random Access Memory Cell , 2020, J. Circuits Syst. Comput..

[20]  Anantha P. Chandrakasan,et al.  Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics , 2017, IEEE Journal of Solid-State Circuits.

[21]  M. Gaillardin,et al.  Modeling Single Event Transients in Advanced Devices and ICs , 2015, IEEE Transactions on Nuclear Science.

[22]  V. K. Tomar,et al.  Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices , 2020, J. Circuits Syst. Comput..

[23]  Sehat Sutardja.  Slowing of Moore's law signals the beginning of smart everything , 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

[24]  Vinay Tomar,et al.  Design of Low Power Half Select Free 10T Static Random-Access Memory Cell , 2020, J. Circuits Syst. Comput..

[25]  Xiaodai Dong,et al.  5G Cellular User Equipment: From Theory to Practical Hardware Design , 2017, IEEE Access.

[26]  Ashish Sachdeva,et al.  Statistical Stability Characterization of Schmitt Trigger Based 10-T SRAM Cell Design , 2020, 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN).

[27]  Shi-Yu Huang,et al.  P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation , 2011, IEEE Journal of Solid-State Circuits.

[28]  Ashish Sachdeva,et al.  Design of 10T SRAM cell with improved read performance and expanded write margin , 2020, IET Circuits Devices Syst..

[29]  Wing-Hung Ki,et al.  Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications , 2020, IEEE Transactions on Electron Devices.

[30]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[31]  Jie Li,et al.  Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[32]  Pinaki Mazumder,et al.  Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  Mohd. Hasan,et al.  Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications , 2018 .

[34]  B.L. Bhuva,et al.  Charge Collection and Charge Sharing in a 130 nm CMOS Technology , 2006, IEEE Transactions on Nuclear Science.

[35]  Ashish Sachdeva,et al.  Design of multi-cell upset immune single-end SRAM for low power applications , 2021 .

[36]  Vida Ilderem,et al.  1.4 5G Wireless Communication: An Inflection Point , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

[37]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[38]  M. Khellah,et al.  A 256-Kb Dual-${V}_{\rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor , 2007, IEEE Journal of Solid-State Circuits.

[39]  Mohammad Sharifkhani,et al.  An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[40]  Y. Bentoutou,et al.  A Real Time EDAC System for Applications Onboard Earth Observation Small Satellites , 2012, IEEE Transactions on Aerospace and Electronic Systems.

[41]  David Blaauw,et al.  SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[42]  T. Saraya,et al.  Comparison and statistical analysis of four write stability metrics in bulk CMOS static random access memory cells , 2015 .

[43]  Meng-Fan Chang,et al.  A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications , 2011, IEEE Journal of Solid-State Circuits.

[44]  Zhi-Hui Kong,et al.  An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[45]  Ahmed M. Eltawil,et al.  AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement , 2017, IET Circuits Devices Syst..

[46]  Soumitra Pal,et al.  9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue , 2016, IEEE Transactions on Device and Materials Reliability.