Quality assurance in complex microsystem development

Quality assurance (QA) is absolutely necessary for the success of any complex microsystem development. However, there is no widely accepted manner in which to implement an efficient quality assurance programme in microsystems research. This paper aims at bridging this gap. The development of complex microsystems differs in a number of ways from traditional space manufacture or related industrial sectors, e.g. the microelectronics industry. The foremost problem is the complexity of manufacture and integration, considering the yield and compatibility of processes. In order to use the full potential of miniaturization by microsystems technology, the systems need to be integrated at the microsystem level, eliminating packages and conventional interfaces. This paper describes the implementation of QA programmes in the development of microsystems, with examples primary from a highly integrated micropropulsion system made from micromachined and bonded silicon wafers. The implementation ranges from process research, over device proof-of-concepts and integration issues, to the delivery of flight hardware. The discussion highlights the distinguishing character of a QA programme for complex microsystems, and details the use of test structures, documentation, process compatibility, reliability and space environment issues, and failure mode evaluation and analysis. In particular, test structures are used to monitor process performance, to demonstrate microsystem functions, and to aid in failure analysis. All development work are carefully planned and formally documented, necessary for reliable manufacture. The main conclusion is that the traditional development hierarchy of engineering models, qualification models, and flight models should be abandoned in favour of a pertinent QA implementation with continuous testing of microsystem features throughout the microsystem development. In this way, the development starts from a microsystem concept and ends in flight hardware, without incurring unnecessary development delays and costs while proving engineering and qualification systems that must be completely redesigned due to integration issues in the final microsystem version. Introduction: The remarkable constraints on autonomy, data-handling and data-transmission capability, power requirements, operational reliability, available space, and mass allowance involved in enabling space missions have always invited massive research and engineering efforts in order to succeed. However, in any engineering or research project of this magnitude, there is risk present: risk threatening the schedule, the technical performance, the project budget, the life and health of those involved, or the scientific, strategic, or commercial output of the mission [1]. Moreover, the space endeavor requires vast resources. Hence, the space community keeps a sharp lookout for possible ways of saving cost, improving performance, or increasing the return of space missions. In these efforts, miniaturization of spacecraft and their subsystems have long been recognized as a vital part. With the advent of microsystems technology, the extreme miniaturization schemes imagined identified this as a key technology in future space missions [2]. The launch cost, a major part of any mission, is directly dependent on the launched mass. Furthermore, the microsystems may also enable missions that would otherwise be impossible. For example, the precision configurations of satellites or deep-space platforms intended for future space research missions require the use of micropropulsion [3] which in turn calls for microsystem technology [4]. In general, any mission that need a multitude of spacecraft, cheap access to space, or a distributed risk will become feasible. The disposable spacecraft concept has suggested robust nanosatellite swarm networks with distributed functions. High-risk nanoprobes for planetary exploration can also be allowed provided they do not infringe too much on the mass budget of the mother spacecraft. Furthermore, surveillance nanosatellites for military or other purposes may be rapidly launched on demand from fighter jets. The microsystem approaches described above share the characteristics of being highly integrated, complex but versatile high-performance systems. Indeed, there are two separate possibilities to incorporate microsystems in space. First, you can use reliable, simple devices, developed for terrestrial applications. By proper design, you will end up with an affordable miniature spacecraft that will be in demand in the cheapaccess-to-space business. On the other hand, you may deliver highly complex microsystems that increase spacecraft performance, dramatically reduces mass, or enables completely new missions. This road is the one pursued at the ÅSTC. Extreme integration of microsystems Six levels of packaging are recognised in the classical integrated circuit (IC) hierarchy, L0–L5 [e.g. 5]. These are IC features (L0), IC chip (L1), chip or multichip package (L2), chip package mounting board, e.g. printed wiring boards (L3), chassis, box, or harness (L4), and the entire system, e.g. a computer (L5). Each level routinely adds interconnects and packages requiring reliable mounting, extra mass, and extra space. Any integration of these levels brings miniaturisation, but in order to truly impact the total mass the integration of at least L0–L4 are required. Figure 1: The illustration of integration levels in a typical system, here a 17 GHz rf telemetry link. L0 and L1 is the micromachined filters, L2 the chip integration of antenna, switches, and filters, L3 includes the beam-steering network (Butler matrix) and additional switches, L4 comprises the complete front-end, and L5 the entire telemetry link system. In the ÅSTC approach the goal is to integrate all levels, possibly barring L5 (the spacecraft). The completed microsystem will be ready for direct mounting, or already be integrated in the spacecraft structure. The high level of integration efficiently reduces the mass and size of interconnections and eliminates intermediate packages. One major challenge in the all-level integration is the tremendous demands on silicon microfabrication process compatibility and reproducibility. In order to meet this challenge, the ÅSTC has initiated a quality assurance program for space microsystems design and manufacture. This program document micromachining processes, design for the space environment, address the space industry’s concerns on microsystem use, and test the performance and robustness of the microsystems. Figure 2: Integration of system functions in multiwafer structures. For instance, using this high level of integration, the robustness of the system functions can be significantly increased. The number of interconnects and package-induced failures naturally decrease. Furthermore, the microsystems technology makes the systems spacious at the feature level, thereby enabling reliability management by introducing multiple redundancy. Figure 2 illustrates the interface elimination idea, and some issues in this endeavour. The multiwafer integrated design of three system functions (colour-coded) that are processed in parallel in several wafers which, in turn, are subsequently bonded together. The separate functions are not testable before integration, and some cannot be reached by probing as integration is completed. On the other hand, a hybrid approach uses testable system components which are integrated and interconnected by more conventional technology. These interconnections and packages normally add magnitudes of mass an volume. Microsystem manufacture process sequence The successful delivery of a single working silicon microsystem forms the natural starting point for a general evaluation of the fabrication process. In order to benefit fully from the promises of massive integration, reliable manufacture of microsystems must be achieved. Here, the process time, fabrication yield, and microsystem cost must be considered. The resources necessary for development must be correctly assessed and valued. In this context, the detailed characteristics of the complete line of processing must be evaluated as a whole, in order to determine which alternate line uses the available resources most efficiently. The process yield of the described fabrication sequence is a major issue for any microsystem manufacture. For IC manufacture, yield models are used with respect to substrate area, line width, routing density, feature size, typical defect size, process cleanliness, and number of process steps [6, 7]. These models are used mainly to estimate the economics of production, relying on large batches of identical devices [8]. In the current state of multifunctional silicon microsystem manufacture, on the other hand, the perspective is primarily technical – what is a feasible line of processing? The complex sequence of a multitude of advanced microfabrication techniques easily results in an overall low yield, suggesting a shaky reliability to the casual observer. However, the development of multifunctional microsystems is still in its infancy. The inherent yield losses are often associated with specific procedures, non-uniformity problems, or random misfortunes. Such occurrences should be identified and evaluated in order to advise on efficient microsystem manufacture and process-risk mitigation. Here, the efficiency of the manufacturing may be substantially influenced by the chosen design of the individual wafers in a multiwafer stack. By proper integration of structures on the wafer level, the number of necessary processes can be minimised. In this manner, the requirements on process compatibility can be relaxed. The wide variety of silicon microfabrication processes will still be available through the bonding of differently processed wafers. In other words, the peak performance of the fabrication process sequence will not be obtained by wafer-scale integ