Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module

In asynchronous RESET signal in DDR3 SDRAM memory module, noise is sensitive at certain specific frequency with low voltage. In this paper, our comprehensive measurement verifies that the RESET signal with specific frequency is changed into “Low” due to the noise (i.e., resonance and crosstalk) that results in system halt. Furthermore, we provide a design guideline to JEDEC memory module PCB sponsors to remedy the noise problem in the RESET signal with providing a specific design topology.

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