An efficient method to evaluate 4 million micro-bump interconnection resistances for 3D stacked 16-mpixel image sensor

We developed an efficient method for evaluating the 4 million micro-bump interconnection resistances of the 3D stacked 16-Mpixel CMOS image sensor by including vertical scanning and readout circuits and extra circuits in both of two substrates for a resistance testing mode, which enables us not only to find failed bumps but also to evaluate the resistances by scanning all micro bumps. We measured the resistances of the interconnections ranging from 50 to 500 kΩ with a resolution of 50kΩ.

[1]  Yoshiaki Takemoto,et al.  A 3D stacked CMOS image sensor with 16Mpixel global-shutter mode and 2Mpixel 10000fps mode using 4 million interconnections , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[2]  Kuo-Shu Kao,et al.  Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[3]  Hiroshi Takahashi,et al.  A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  D. Kwong,et al.  Study of 15µm pitch solder microbumps for 3D IC integration , 2009, 2009 59th Electronic Components and Technology Conference.

[5]  Takashi Machida,et al.  An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage , 2012, 2012 IEEE International Solid-State Circuits Conference.

[6]  Kobayashi Kenji,et al.  A 3D stacked CMOS image sensor with 16Mpixel global-shutter mode using 4 million interconnections , 2015 .

[7]  Yoshiaki Takemoto,et al.  A rolling-shutter distortion-free 3D stacked image sensor with −160dB parasitic light sensitivity in-pixel storage node , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  R. Berger,et al.  Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[9]  John H. Lau,et al.  Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps , 2009, 2009 59th Electronic Components and Technology Conference.

[10]  Vempati Srinivasa Rao,et al.  Process Development and Reliability of Microbumps , 2010, IEEE Transactions on Components and Packaging Technologies.

[11]  E Beyne,et al.  Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking , 2010, 3rd Electronics System Integration Technology Conference ESTC.

[12]  Yoshiaki Takemoto,et al.  Reliability Results of 4 million Micro Bump Interconnections of 3D Stacked 16 M Pixel Image Sensor , 2015 .

[13]  Shoji Kawahito,et al.  A 2.7e- temporal noise 99.7% shutter efficiency 92dB dynamic range CMOS image sensor with dual global shutter pixels , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).