A Reconfigurable Viterbi Decoder for a Communication Platform

A new large constraint length, soft decision Viterbi decoder fabric is presented for deployment using platform based system on chip methodologies. The decoder can be reconfigured for standards such as CDMA2000, WCDMA (UMTS), ADSL, IEEE 802.11, and GSM. Maximum resource allocation and performance is achieved by reusing components within turbo decoder base array. This cross platform Viterbi decoder is reconfigurable between different trellis types, constraint lengths and rates making it ideal for a unified multi-standard telecommunication platform. In addition, the authors also propose a novel technique for dynamic reconfiguration in order to achieve faster context switching between different mappings. The reconfigurable fabric is implemented as a subset of turbo decoder array on a 180 nm UMC process technology

[1]  Kung Yao,et al.  Systolic array processing of the Viterbi algorithm , 1989, IEEE Trans. Inf. Theory.

[2]  Paul H. Siegel,et al.  Area-efficient architectures for the Viterbi algorithm. I. Theory , 1993, IEEE Trans. Commun..

[3]  C. Rader Memory Management in a Viterbi Decoder , 1981, IEEE Trans. Commun..

[4]  Paul H. Siegel,et al.  Area-Efficient Architectures for the Viterbi Algorithm-Part I : Theory , 2004 .

[5]  Tughrul Arslan,et al.  Improved memory strategy for logmap turbo decoders , 2005, Proceedings 2005 IEEE International SOC Conference.

[6]  A. N. Willson,et al.  Low-power Viterbi decoder for CDMA mobile terminals , 1998 .

[7]  J. Kumar,et al.  A processor for graph search algorithms , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  Ran-Hong Yan,et al.  A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).