Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook

This article provides a pragmatic survey on the state of the art in GALS architectural techniques, design flows, and applications. The authors also prescribe several industrial inventions and changes in methodology, tools, and design flow that would improve GALS-based integration of IP blocks.

[1]  Edith Beigné,et al.  Design of on-chip and off-chip interfaces for a GALS NoC architecture , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[2]  Mark R. Greenstreet,et al.  Efficient self-timed interfaces for crossing clock domains , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[3]  Ran Ginosar,et al.  An asynchronous router for multiple service levels networks on chip , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[4]  Christian Bernard,et al.  A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  Kenneth Y. Yun,et al.  Pausible clocking: a first step toward heterogeneous systems , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[6]  Simon W. Moore,et al.  Demystifying Data-Driven and Pausible Clocking Schemes , 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).

[7]  Daniel Marcos Chapiro,et al.  Globally-asynchronous locally-synchronous systems , 1985 .

[8]  Eckhard Grass,et al.  System integration by request-driven GALS design , 2006 .

[9]  Ran Ginosar.  Fourteen ways to fool your synchronizer , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[10]  Steven M. Nowick,et al.  Low-latency asynchronous FIFO's using token rings , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[11]  Luca Benini,et al.  On-Chip Communication Architectures: System on Chip Interconnect , 2008 .

[12]  N. Felber,et al.  Improving DPA security by using globally-asynchronous locally-synchronous systems , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[13]  Ad M. G. Peeters,et al.  Adding synchronous and LSSD modes to asynchronous circuits , 2003, Microprocess. Microsystems.

[14]  Wolfgang Fichtner,et al.  GALS at ETH Zurich: success or failure? , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[15]  Paul Wielage,et al.  Clock synchronization through handshake signalling , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[16]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[17]  Jens Sparsø,et al.  An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip , 2005, 2005 International Symposium on System-on-Chip.

[18]  Ran Ginosar,et al.  Data synchronization issues in GALS SoCs , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

[19]  Zhiyi Yu,et al.  Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles , 2006, 2006 International Conference on Computer Design.

[20]  Emil Talpes,et al.  Toward a multiple clock/voltage island design style for power-aware processors , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Wolfgang Fichtner,et al.  Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).