A Device Level Auto Place And Wire Methodology For Analog And Digital Masterslices

A DEVICE LEVEL AUTO PLACE AND WIRE METHODOLOGY designed t o minimize manual intervention will be described. Placement and wiring is automatically given a logical description of the circuit topology at the device level. Standard cells can be used for a part of the chip with a remainder of the chip circuitry included in the logical description. All device placement is generated with a Monte Carlo or simulated annealing algorithm. Wiring is generated automatically by a maze-runner algorithm. Chips designed by this method achieve 75% chip density for a 1000element circuit with over 1OOMHz signals, with circuit layouts completed in 5 days.