FFT Architectures for Real-Valued Signals Based on Radix-$2^{3}$ and Radix-$2^{4}$ Algorithms

This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals. The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths. The imaginary parts of the computations replace the redundant operations in the modified flow graph. New butterfly structures are designed to handle the hybrid datapaths. The proposed hybrid datapath leads to a general approach which can be extended to all radix- 2n based FFT algorithms. Further, architectures with arbitrary level of parallelism can be derived using the folding methodology. Novel 2-parallel and 4-parallel architectures are presented for radix- 23 and radix- 24 algorithms. The proposed architectures maximize the utilization of hardware components with no redundant computations. The proposed radix- 23 and radix- 24 architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix- 24 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements.

[1]  K. Parhi,et al.  Parallel - pipelined radix-22 FFT architecture for real valued signals , 2010, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers.

[2]  Hanho Lee,et al.  A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems , 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[3]  Shousheng He,et al.  Designing pipeline FFT processor for OFDM (de)modulation , 1998, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167).

[4]  A. Chandrakasan,et al.  Energy-efficient DSPs for wireless sensor networks , 2002, IEEE Signal Process. Mag..

[5]  Keshab K. Parhi,et al.  A Pipelined FFT Architecture for Real-Valued Signals , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Alan V. Oppenheim,et al.  Discrete-time signal processing (2nd ed.) , 1999 .

[7]  S.F. Reddaway,et al.  Ultra-high performance, low-power, data parallel radar implementations , 2005, IEEE International Radar Conference, 2005..

[8]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[9]  Keshab K. Parhi,et al.  Seizure Prediction With Spectral Power of EEG Using Cost-Sensitive Support Vector Machines , 2010 .

[10]  Douglas L. Jones,et al.  Real-valued fast Fourier transform algorithms , 1987, IEEE Trans. Acoust. Speech Signal Process..

[11]  A.P. Chandrakasan,et al.  Energy-aware architectures for a Real-Valued FFT implementation , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[12]  H. Ziegler.  A fast Fourier transform algorithm for symmetric real-valued series , 1972 .

[13]  H. V. Sorensen,et al.  An efficient FFT algorithm for real-symmetric data , 1992, [Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[14]  Keshab K. Parhi,et al.  Parallel pipelined FFT architectures with reduced number of delays , 2012, GLSVLSI '12.

[15]  Keshab K. Parhi,et al.  Pipelined Parallel FFT Architectures via Folding Transformation , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Hsiang-Feng Chi,et al.  A cost-effective memory-based real-valued FFT and Hermitian symmetric IFFT processor for DMT-based wire-line transmission systems , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[17]  Jean-Bernard Martens,et al.  Discrete Fourier transform algorithms for real valued sequences , 1984 .

[18]  Bevan M. Baas,et al.  A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.

[19]  Winthrop W. Smith.  Handbook of Real-Time Fast Fourier Transforms , 1995 .

[20]  Anantha Chandrakasan,et al.  Energy-aware architectures for a real-valued FFT implementation , 2003, ISLPED '03.

[21]  Young-Cheol Park,et al.  An efficient DMT modem for the G.LITE ADSL transceiver , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[22]  Keshab K. Parhi,et al.  Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation , 1992 .

[23]  K. M. M. Prabhu,et al.  Radix-2 decimation-in-frequency algorithm for the computation of the real-valued FFT , 1999, IEEE Trans. Signal Process..

[24]  Keshab K. Parhi,et al.  Synthesis of control circuits in folded pipelined DSP architectures , 1992 .