A DTCNN circuit proposal for pixel-level snakes

A VHDL description of a DTCNN circuit for pixel-level snakes is given. This is the first of successive steps in a top-down design flow towards a final physical implementation. The complexity of the application leads us to make use of a multilayer DTCNN with cyclic time variable cloning templates. In order to make a feasible physical implementation, the basic concepts of the CNN Universal Machine (CNNUM) have been adopted: distributed memory and programming templates. In addition, some other approaches like the use of 2Q multipliers are followed. The validity of the proposed structure is illustrated by simulations of a 9/spl times/9 network.