A carry-free 54 b/spl times/54 b multiplier using equivalent bit conversion algorithm
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[1] M. Nagamatsu,et al. A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology , 1991 .
[2] Atsuki Inoue,et al. A 4.1-ns Compact 54 54-b Multiplier Utilizing Sign-Select Booth Encoders , 1997 .
[3] A. Inoue,et al. A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[4] G. Goto,et al. A 54*54-b regularly structured tree multiplier , 1992 .
[5] K. Mashiko,et al. An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture , 1996 .
[6] Michitaka Kameyama,et al. A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic , 1995 .