A Charge-Based Architecture for Energy-Efficient Vector-Vector Multiplication in 65nm CMOS

In this work, a charge-based energy-efficient architecture for computing vector-vector multiplications (VVM) is presented. Using an array of capacitors, the inner product of vectors is quantitatively computed as the total charge injected onto the array. By scaling the capacitance to the thermal noise (kTC) limit, this computation can be done efficiently on the order of a few picoJoules (pJ). Furthermore, this charge is then converted into a pulse-density modulated binary output over time through a first-order delta-sigma converter, giving a trade-off of output precision and computation time. This design was fabricated in a 65nm CMOS process and measured to compute 6-bit MACs with a throughput of 350KOPs, and an overall efficiency of 14.6GOP/W at 5-bit precision. Moreover, the computation done on the array in the analog domain, has an efficiency of 284.4GOP/W.

[1]  David J. Brown,et al.  Toward Energy-Efficient Computing , 2010, ACM Queue.

[2]  René Schüffny,et al.  Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS , 2014, Front. Neurosci..

[3]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[4]  Youngcheol Chae,et al.  Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator , 2009, IEEE Journal of Solid-State Circuits.

[5]  G. Cauwenberghs,et al.  1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor , 2012, IEEE Sensors Journal.

[6]  Heemin Y. Yang.  A time-based energy-efficient analog-to-digital converter , 2005, IEEE Journal of Solid-State Circuits.

[7]  Andreas Kaiser,et al.  Very low-voltage fully differential amplifier for switched-capacitor applications , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[8]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[9]  Paul E. Hasler,et al.  A Highly Dense, Low Power, Programmable Analog Vector-Matrix Multiplier: The FPAA Implementation , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[10]  Adolfo Steiger-Garção,et al.  Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Andreas Kaiser,et al.  Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping , 2001, IEEE J. Solid State Circuits.

[12]  Andreas G. Andreou,et al.  Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer , 1997 .

[13]  Esther Rodríguez-Villegas,et al.  A 1.2-V 140-nW 10-bit Sigma–Delta Modulator for Electroencephalogram Applications , 2008, IEEE Transactions on Biomedical Circuits and Systems.

[14]  Gert Cauwenberghs,et al.  Charge-mode parallel architecture for vector-matrix multiplication , 2001 .

[15]  R. Genov,et al.  480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition , 2007, IEEE Journal of Solid-State Circuits.

[16]  W. Sansen,et al.  A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[17]  René Schüffny,et al.  A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits , 2014, IEEE Transactions on Biomedical Circuits and Systems.