Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔfractional-N synthesizer

A 19 mW highly integrated GPS receiver with a ΣΔfractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier (LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure<2 dB, channel gain=108 dB (LNA1 included), image rejection>36 dB, and −108 dBc/Hz @ 1 MHz phase noise offset from the carrier. The carrier noise ratio (C/N) can reach 41 dB at an input power of −130 dBm. The chip operates over a temperature range of [−40, 120] °C and ±5% tolerance over the CMOS technology process.

[1]  Zhibiao Shao,et al.  A generalized MASH architecture in fractional-N synthesizer , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

[2]  S. Das,et al.  A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio , 2006, IEEE Journal of Solid-State Circuits.

[3]  Zhihua Wang,et al.  Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer , 2007, DATE.

[4]  Robert A. Scholtz,et al.  Performance Analysis of , 1998 .

[5]  Daniel N. Aloi,et al.  A Methodology for the Evaluation of a GPS Receiver Performance in Telematics Applications , 2007, IEEE Transactions on Instrumentation and Measurement.

[6]  Jacob A. Abraham,et al.  Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[7]  Zhihua Wang,et al.  Modeling and Simulation to the Design of ΣΔ Fractional-N Frequency Synthesizer , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[8]  Ho-Jun Song,et al.  Design and implementation of L1-band C/A-code GPS RF front-end chip , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[9]  B.-S. Song,et al.  A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator , 2000, IEEE Journal of Solid-State Circuits.

[10]  Dennis M. Akos,et al.  Comparison of direct and downconverted digitization in GPS receiver front end designs , 1996, 1996 IEEE MTT-S International Microwave Symposium Digest.

[11]  K. Halonen,et al.  Behavioral simulation of fractional-N PLL frequency synthesizers: Phase approach , 2008, 2008 11th International Biennial Baltic Electronics Conference.

[12]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[13]  A. Molnar,et al.  A single-chip quad-band (850/900/1800/1900 MHz) direct-conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-N synthesizer , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[14]  Tsung-Hsien Lin,et al.  A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[15]  A. Peczalski.  RF/analog/digital SOI technology for GPS receivers and other systems on a chip , 2002, Proceedings, IEEE Aerospace Conference.

[16]  H.H. Lee,et al.  A study on the in-orbit environment of a GPS receiver for low/medium altitude satellites , 2008, 2008 6th IEEE International Conference on Industrial Informatics.

[17]  Moeness G. Amin,et al.  Performance Analysis of GPS Receivers in Non-Gaussian Noise Incorporating Precorrelation Filter and Sampling Rate , 2008, IEEE Transactions on Signal Processing.