The paper describes the design of a pipelined analog-to-digital converter (ADC), featuring 14 bit resolution and 100 MS/s conversion speed, with 2 Vpp input range and 3.3 V power supply. The target was an INL/DNL error within 0.5 LSB of INL/DNL, with a low power consumption. The optimization of the converter architecture, i.e. the partitioning of the ADC's resolution among the stages of the pipeline chain, was carried out by means of a behavioral model. A single-stage telescopic OTA providing a large GB W product at a moderate power consumption was used in the first stages. Capacitor shuffling calibration was introduced in order to eliminate the effects of the capacitors mismatch on the converter THD. The chip was implemented in a 0.18 μm CMOS technology. The power dissipation is 150 mW and the simulated SFDR is 84 dB.