A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM

In this paper we introduce a 14-core application processor for multimedia mobile applications, implemented in 40 nm, with a 222 mW H.264 full high-definition (full-HD) video engine, a 124 mW 40 M-polygons/s 3D/2D graphics engine, and a video/audio multiprocessor for various Codecs and image processing. The application processor has 25 power domains to achieve coarse-grain power gating for adjusting to the required performance of wide range of multimedia applications. The simple on-chip power switch circuits perform less than 1 μs switching while reducing rush current. Furthermore, the Stacked Chip SoC (SCS) technology enables rewiring to the DRAM chip during assembly/packaging phase using a wire with 10 μm minimum pitch on Re-Distribution Layer (RDL) using electroplating. The peak memory bandwidth is 10.6 GB/s with an x512b SCS-DRAM interface, and the power consumption of this interface is 3.9 mW at 2.4 GB/s workload.

[1]  T. Hattori,et al.  Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[2]  Kenji Hirose,et al.  A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[3]  Hiroshi Ueda,et al.  A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits , 2010, IEEE Journal of Solid-State Circuits.

[4]  H. Yamamoto,et al.  A 45nm single-chip application-and-baseband processor using an intermittent operation technique , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  S. Raisamo,et al.  From , 2020, The Solace Is Not the Lullaby.

[6]  K. Kondo,et al.  A 160Gb/s interface design configuration for multichip LSI , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[7]  Tatsuya Mori,et al.  A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications , 2009, IEEE Journal of Solid-State Circuits.

[8]  Liang-Gee Chen,et al.  A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[9]  Uming Ko,et al.  A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.