We present a new approach to direct mapping of arbitrary combinational RTL (Register Transfer Level) components onto SRAM-based FPGAs. This method consists of a core generator which implements multiplexors and multiplexor structures directly onto FPGAs. The implementation incorporates the mapping, the decomposition and placement of the whole module. The method is neither limited to a specific FPGA nor to a specific vendor because the generator is based on a generic logic block model. Additionally, any combinational module can be described as a multiplexor structure. Taking this fact into account the multiplexor generator has been extended by a user interface in order to describe the structure of any combinational and parameterizable module. This leads to very fast development cycles of arbitrary modules. Some modules like multipliers, shifters and dividers have been implemented using this general approach. Compared to a previously published dedicated multiplier generator this implementation is much faster and yields better results in terms of logic cell consumption as well as critical path length.
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