FITTest BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties

In the paper, the FITTest_BENCH06 set of synthetic benchmark circuits is presented for the evaluation of diagnostic methods and tools. The structure of benchmark circuits together with their diagnostic properties is described. The set consists of 31 circuits at various levels of complexity (2000, 10000, 28000, 100000, 150000 and 300000 gates). Four circuits with different diagnostic properties are available for each level of circuit complexity (fault coverage is approx. 0%, 33%, 66% and 100%). The benchmark circuits are available both at the register transfer level and the gate level. In addition to the benchmark set, a method is described that was used to develop benchmark circuits with required complexity and diagnostic properties

[1]  Wayne Wei-Ming Dai,et al.  A Method for Generation Random Circuits and Its Application to Routability Measurement , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[2]  Jonathan Rose,et al.  Synthetic circuit generation using clustering and iteration , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Josef Strnadel,et al.  Evolutionary Design of Synthetic RTL Benchmark Circuits , 2004 .

[4]  Josef Strnadel VIRTA: VIRTUAL PORT BASED REGISTER-TRANSFER LEVEL TESTABILITY ANALYSIS AND IMPROVEMENTS , 2005 .

[5]  Zdenek Kotásek,et al.  Automatic discovery of RTL benchmark circuits with predefined testability properties , 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

[6]  Jan Van Campenhout,et al.  Synthetic Benchmark Circuits for Timing-driven Physical Design Applications. , 2002 .

[7]  Michel Minoux,et al.  Generation of very large circuits to benchmark the partitioning of FPGA , 1999, ISPD '99.

[8]  Justin E. Harlow,et al.  Overview of Popular Benchmark Sets , 2000, IEEE Des. Test Comput..

[9]  Kazuo Iwama,et al.  Random benchmark circuits with controlled attributes , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[10]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[11]  Jonathan Rose,et al.  Automatic generation of synthetic sequential benchmark circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .