FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems

Abstract A series FinFET based non-volatile logic gates with multiple logic functions defined by embedded non-volatile states are proposed for the first time and demonstrated in advanced CMOS technology platform. The device channels in the proposed CMOS logic gate is controlled by a metal floating gate coupled by slot contacts uniquely available in the FinFET process employed in this study. The new logic gate with non-volatile states only enable reconfiguration ability in a Boolean computing unit at a gate level aimed for adaptive and specialized systems in the AI era. Furthermore, the extended applications in tunable ring oscillators for multi-functional IOT modules are successfully demonstrated in this study.

[1]  V. A. L. Roy,et al.  Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism , 2013, Scientific Reports.

[2]  Chenming Hu,et al.  Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion , 2002, IEEE Electron Device Letters.

[3]  W. Ditto,et al.  Construction of a Chaotic Computer Chip , 2009 .

[4]  G. C. Sirakoulis,et al.  A Novel Design and Modeling Paradigm for Memristor-Based Crossbar Circuits , 2012, IEEE Transactions on Nanotechnology.

[5]  S.C. Rustagi,et al.  Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications , 2008, IEEE Transactions on Electron Devices.

[6]  Raju Khubchandani.  A fast test to generate flash memory threshold voltage distribution map , 1999, Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing.

[7]  Dong Ik Suh,et al.  A Single Magnetic Tunnel Junction Representing the Basic Logic Functions—NAND, NOR, and IMP , 2015, IEEE Electron Device Letters.

[8]  William D. Brown,et al.  Basics of Nonvolatile Semiconductor Memory Devices , 1998 .

[9]  Steve S. Chung,et al.  The performance and reliability enhancement of ETOX p-channel flash EEPROM cell with p-doped floating-gate , 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

[10]  Yue-Der Chih,et al.  Twin mode NV logic gates for high speed computing system on 16nm FINFET CMOS logic process , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[11]  Hongwei Qu,et al.  Hamster female protein. A divergent acute phase protein in male and female Syrian hamsters , 1983, The Journal of experimental medicine.

[12]  Y. Chih,et al.  Differential multiple-time-programmable memory cells by laterally coupled floating metal gate fin field-effect transistors , 2017 .

[13]  Y. King,et al.  Effect of three-dimensional current distribution on characterizing parasitic resistance of FinFETs , 2016 .

[14]  H. Yin,et al.  Fabrication of Bulk-Si FinFET using CMOS compatible process , 2012 .

[15]  Kazuo Yano,et al.  Room-temperature single-electron memory , 1994 .

[16]  Jagan Singh Meena,et al.  Overview of emerging nonvolatile memory technologies , 2014, Nanoscale Research Letters.

[17]  Meng Chuan Lee,et al.  Technical solutions to mitigate reliability challenges due to technology scaling of charge storage NVM , 2013 .

[18]  Akshay Kumar,et al.  Smart Robotic Assistant , 2015, 2015 IEEE Region 10 Symposium.

[19]  M. R. M. Rizk,et al.  A new approach for obtaining all logic gates using Chua's Circuit: Advantages and disadvantages , 2012, 2012 International Conference on Computer and Communication Engineering (ICCCE).

[20]  Gerhard R. Joubert,et al.  Parallel Computing: On the Road to Exascale , 2016 .

[21]  Dong Sun,et al.  Development of an FPGA-Based Motion Control ASIC for Robotic Manipulators , 2006, 2006 6th World Congress on Intelligent Control and Automation.

[22]  Jun Deguchi,et al.  A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing , 2017, IEEE Journal of Solid-State Circuits.

[23]  Kwabena Boahen,et al.  Optic nerve signals in a neuromorphic chip II: testing and results , 2004, IEEE Transactions on Biomedical Engineering.

[24]  Runze Han,et al.  Demonstration of Logic Operations in High-Performance RRAM Crossbar Array Fabricated by Atomic Layer Deposition Technique , 2017, Nanoscale Research Letters.

[25]  Sudeshna Sinha,et al.  Chaogates: morphing logic gates that exploit dynamical patterns. , 2010, Chaos.

[26]  Sudeshna Sinha,et al.  Chaos computing: ideas and implementations , 2007, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences.

[27]  N Alteheld,et al.  Towards the bionic eye--the retina implant: surgical, opthalmological and histopathological perspectives. , 2007, Acta neurochirurgica. Supplement.

[28]  John Paul Mueller,et al.  Artificial Intelligence For Dummies , 2018 .

[29]  Isamu Kajitani,et al.  Evolvable Hardware for Generalized Neural Networks , 1997, IJCAI.

[30]  Andre Wavre.  Application of Integrated Circuits to Industrial Control Systems with High-Noise Environments , 1969 .

[31]  Guangyi Wang,et al.  A Locally Active Memristor and Its Application in a Chaotic Circuit , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.