Accessing Manufacturing Yield for Gamma Wafer Sawing Processes in COG Packaging

The technology of thin film transistor liquid crystal display (LCD) has become more popular due to great demand for worldwide consumer electronic products. Driver integrated circuit (IC) is a critical device that is embedded sophisticated circuits to drive panels. Since narrow border design on display products is current trend, dimensions of driver ICs are shrunken. In the high-density LCD driver ICs, the operation of wafer sawing is essential and needs accurate yield assessment. However, inevitable process variance changes could arise from sawing machine, material, operation, and workmanship, and may not be detected within short time. Conventionally, manufacturing yield is evaluated applying typical yield measure index method under the assumptions that the processes are stable and normal. To assess manufacturing yield for Gamma wafer sawing processes more accurately, we present a modified yield measure index method. Using the proposed method, the magnitudes of the undetected variance change, which are functions of the detection power of the ${{S}^{2}}$ chart, are incorporated into the evaluation of manufacturing yield. In addition, we demonstrate, mathematically, that the accommodation would not be affected by the scale parameter of Gamma distribution. For illustration purpose, a real-world case in a wafer sawing factory which is located on the Science-based Industrial Park in Hsinchu, Taiwan, is presented.

[1]  Davis R. Bothe Statistical Reason for the 1.5 sigma Shift , 2002 .

[2]  Wen-Yuan Chen,et al.  Three-step approach for wafer sawing lane inspection , 2009 .

[3]  W. L. Pearn,et al.  Capability adjustment for gamma processes with mean shift consideration in implementing Six Sigma program , 2008, Eur. J. Oper. Res..

[4]  Douglas C. Montgomery,et al.  Introduction to Statistical Quality Control , 1986 .

[5]  Dong Ho Park,et al.  Estimation of capability index based on bootstrap method , 1996 .

[6]  Victor E. Kane,et al.  Process Capability Indices , 1986 .

[7]  Israel Koren,et al.  A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits , 1993, IEEE Trans. Computers.

[8]  Roger M. Sauter,et al.  Introduction to Statistical Quality Control (2nd ed.) , 1992 .

[9]  Wen Lea Pearn,et al.  Tool replacement for production with a low fraction of defectives , 2006 .

[10]  J. Bernstein,et al.  Reliability Study of High-Density EBGA Packages Using the Cu Metallized Silicon , 2008, IEEE Transactions on Components and Packaging Technologies.

[11]  M. Tsai,et al.  Testing and Evaluation of Silicon Die Strength , 2007, IEEE Transactions on Electronics Packaging Manufacturing.

[12]  Charles H. Stapper Improved Yield Models for Fault-Tolerant Memory Chips , 1993, IEEE Trans. Computers.

[13]  Charles H. Stapper LSI yield modeling and process monitoring , 2000, IBM J. Res. Dev..

[14]  A. Jalar,et al.  Effect of laminated wafer toward dicing process and alternative double pass sawing method to reduce chipping , 2006, IEEE Transactions on Electronics Packaging Manufacturing.

[15]  Thomas Pyzdek,et al.  PROCESS CAPABILITY ANALYSIS USING PERSONAL COMPUTERS , 1992 .

[16]  Chien-Wei Wu,et al.  Quality-yield measure for production processes with very low fraction defective , 2004 .

[17]  Evaluation of die edge cracking in flip-chip PBGA packages , 2003 .

[18]  Davis R. Bothe,et al.  Statistical Reason for the 1.5σ Shift , 2002 .