A successful HBM ESD protection circuit for micron and sub-micron level CMOS

Abstract A successful ESD protection circuit depends on a clear understanding of the process parameters and design rules of a given fabrication process. This work will show an ESD protection scheme that protects CMOS well as minimum feature sizes ranging from micron to sub-micron scales. The primary protection device utilizes an SCR structure available from a N-Well CMOS process in conjunction with a series N-Well resistor. ESD immunity of > 2kV has been demonstrated on state of the art ASIC arrays using these structures.