论文信息 - Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization

Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization

This paper presents the results from research work done in the field of reconfigurable architectures and systems. Dynamic and partial reconfiguration has mainly been investigated as a way to configure functionalities in hardware on-demand, controlled either by the user or by the system itself. This paper presents work that was aimed at applying hardware reconfiguration even for run-time adaptation of functional implementation in order to enable self-optimization of power and performance according to the run-time specific requirements of the application.

[1] Jürgen Becker,et al. On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[2] Jürgen Becker,et al. Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[3] Neil Joseph Steiner. A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs , 2002 .

[4] Jürgen Becker,et al. Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems , 2007, ReCoSoC.

[5] Jürgen Becker,et al. On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives , 2006, SBCCI '06.