FPGA system-level based design of multi-axis ADRC controller

Abstract The real-time control of high precision multi-axis system with modeling uncertainties and strong nonlinear coupling dynamics is a demanding task for conventional multivariable control applications. To this end, this research addresses the design of Active Disturbance Rejection Control (ADRC) for multi-axis system and its implementation in the Field Programmable Gate Array (FPGA) platform. For the ADRC algorithm, the minimum plant model information is necessary, and that enables a strong system robustness and adaptability under modeling uncertainty, coupling effects and external disturbances. Distinct from the traditional Very high speed integrated circuit Hardware Description Language (VHDL) design, the proposed FPGA implementation of ADRC is based on the system level design and it considerably reduces the design cycle. Moreover, the optimal fixed-point realization and controller architecture are selected as a tradeoff between control performances and FPGA resource occupancy. The ADRC tracking performances, robustness and stability are confirmed through the frequency domain analysis and experimentally validated on three-axis didactic radar antenna control system in different working conditions.