论文信息 - Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

In this letter, we propose a simplified channel stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage (Vth) setting method that all the SSTs on each layer are set to targeted the Vth values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAD simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the Vth values of SSTs are set to the targeted Vth values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the Vth values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

[1] Shih-Hung Chen,et al. Overview of 3D NAND Flash and progress of vertical gate (VG) architecture , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

[2] Y. Iwata,et al. Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices , 2006, 2009 Symposium on VLSI Technology.

[3] Chih-Yuan Lu,et al. A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability , 2010, 2010 IEEE International Memory Workshop.

[4] Myounggon Kang,et al. Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray , 2012, IEEE Transactions on Electron Devices.

[5] K. Hsieh,et al. A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device , 2010, 2010 Symposium on VLSI Technology.

[6] Byung-Gook Park,et al. Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM) , 2013, 2013 IEEE International Electron Devices Meeting.

[7] Byung-Gook Park,et al. Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory , 2011, IEEE Transactions on Electron Devices.

[8] Dong Woo Kim,et al. Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory , 2006, 2009 Symposium on VLSI Technology.