Algorithms for routing and testing routability of planar VLSI layouts

This paper studies the problem of routing wires in a grid among features on one layer of a VLSI chip, when a sketch of the layer is given. A sketch specifies the positions of features and the topology of the interconnecting wires. We give polynomial-time algorithms that (1) determine the routability of a sketch, and (2) produce a routing of a sketch that optimizes both individual and total wire length. These algorithms subsume most of the polynomial-time algorithms in the literature for planar routing and routability testing in the rectilinear grid model. We also provide an explicit construction of a database, called the rubber-band equivalent, to support computation involving the layout topology.