An Optimization Approach to Single-Bit Quantization

This paper presents an optimization approach to single-bit quantization. The paper starts by redefining single-bit quantization as a maximum-likelihood sequence detection problem and by showing that the Viterbi algorithm is its optimal solution. It also shows that the conventional ¿¿ converter implements a greedy solution to the same optimization problem. There is, moreover, a continuum of solutions with different degrees of complexity between the ¿¿s and the Viterbi solution. The paper details one such intermediate-complexity solution (based on the M-algorithm) and demonstrates that with an appropriate noise shaping filter it achieves a performance very close to the optimal Viterbi solution. The paper concludes by presenting two procedures for designing effective noise shaping filters.

[1]  Mohammed Ismail,et al.  Sigma-Delta Solutions for Future Wireless Handields , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[2]  Pieter Rombouts,et al.  Mismatch Insensitive Double-Sampling Quadrature Bandpass $\Sigma\Delta$ Modulation , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Ian Galton,et al.  Delta-sigma data conversion in wireless transceivers , 2002 .

[4]  Zhongming Shi,et al.  Sigma-delta ADC and DAC for digital wireless communication , 1999, 1999 IEEE Radio Frequency Integrated Circuits Symposium (Cat No.99CH37001).

[5]  F. Harris,et al.  On synthesizing high speed sigma-delta DACs by combining the outputs of multiple low speed sigma-delta DACs , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

[6]  Tor Aulin,et al.  Digital Phase Modulation , 1986, Applications of Communications Theory.

[7]  John B. Anderson,et al.  Limited search trellis decoding of convolutional codes , 1989, IEEE Trans. Inf. Theory.

[8]  J.F. Jensen,et al.  A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping , 2005, IEEE Journal of Solid-State Circuits.

[9]  Toby Berger,et al.  Tree encoding of Gaussian sources , 1974, IEEE Trans. Inf. Theory.

[10]  Oliver M. Collins,et al.  An All-Digital Transmitter With a 1-Bit DAC , 2007, IEEE Transactions on Communications.

[11]  Seyed Mojtaba Atarodi,et al.  A 1.8-v high-speed 13-bit pipelined analog to digital converter for digital IF applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[12]  Robert M. Gray,et al.  An Algorithm for the Design of Labeled-Transition Finite-State Vector Quantizers , 1985, IEEE Trans. Commun..

[13]  Rolf Johannesson,et al.  Fundamentals of Convolutional Coding , 1999 .

[14]  Cheng-Chieh Lee,et al.  Trellis-based scalar vector quantization of sources with memory , 2000, IEEE Trans. Inf. Theory.

[15]  Robert M. Gray,et al.  Simulation of Vector Trellis Encoding Systems , 1986, IEEE Trans. Commun..

[16]  Frederick Jelinek.  Tree encoding of memoryless time-discrete sources with a fidelity criterion , 1969, IEEE Trans. Inf. Theory.

[17]  Richard Schreier,et al.  An empirical study of high-order single-bit delta-sigma modulators , 1993 .

[18]  Fuwen Yang,et al.  An H∞ Approach for Robust Calibration of Cascaded Sigma Delta Modulators , 2006, Proceedings of the 45th IEEE Conference on Decision and Control.

[19]  Rolf Johannesson,et al.  Systematic Feed-Forward Convolutional Encoders Are Better than Other Encoders with an M-Algorithm Decoder , 1998, IEEE Trans. Inf. Theory.

[20]  Nariman Farvardin,et al.  A study of vector quantization for noisy channels , 1990, IEEE Trans. Inf. Theory.

[21]  David L. Neuhoff,et al.  Quantization , 2022, IEEE Trans. Inf. Theory.

[22]  R.W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS , 2006, IEEE Journal of Solid-State Circuits.

[23]  Fuwen Yang,et al.  An $H_{\infty}$ Approach for Robust Calibration of Cascaded Sigma–Delta Modulators , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Robert W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS , 2006 .

[25]  Franco Maloberti,et al.  A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[26]  G. Temes.  Delta-sigma data converters , 1994 .

[27]  S. Wilson,et al.  Trellis encoding of continuous-amplitude memoryless sources (Corresp.) , 1977, IEEE Trans. Inf. Theory.

[28]  Francisco Colodro Ruiz,et al.  New multirate bandpass sigma-delta modulators , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  Pieter Rombouts,et al.  Efficient Multibit Quantization in Continuous-Time $\Sigma \Delta$ Modulators , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[30]  E. Charry,et al.  A 5 GHz continuous time sigma-delta modulator implemented in 0.4 /spl mu/m InGaP/InGaAs HEMT technology , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[31]  Terri S. Fiez,et al.  A spurious-free delta-sigma DAC using rotated data weighted averaging , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[32]  Min Wang,et al.  Trellis-coded quantization designed for noisy channels , 1994, IEEE Trans. Inf. Theory.

[33]  Susan Luschas,et al.  Radio frequency digital-to-analog converter , 2004, IEEE Journal of Solid-State Circuits.

[34]  Nader Moayeri,et al.  Trellis coded vector quantization , 1992, IEEE Trans. Commun..

[35]  Teng-Hung Chang,et al.  Fourth-Order Cascaded $\Sigma \Delta$ Modulator Using Tri-Level Quantization and Bandpass Noise Shaping for Broadband Telecommunication Applications , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[36]  Jouko Vankka,et al.  Spur reduction techniques in sine output direct digital synthesis , 1996, Proceedings of 1996 IEEE International Frequency Control Symposium.

[37]  A. Gutierrez,et al.  Ultra wideband digital to analog conversion based on advanced InP DHBT technology , 2005, IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05..

[38]  Yong Ping Xu,et al.  A novel noise-shaping DAC for multi-bit sigma-delta modulator , 2006, IEEE Trans. Circuits Syst. II Express Briefs.

[39]  Bernard Mulgrew,et al.  On the design of high-performance wide-band continuous-time sigma-delta converters using numerical optimization , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[40]  V. S. Reinhardt,et al.  Sine output DDSs. A survey of the state of the art , 1998, Proceedings of the 1998 IEEE International Frequency Control Symposium (Cat. No.98CH36165).