MOSFET scaling limits determined by subthreshold conduction
暂无分享,去创建一个
[1] Paul S. Ho,et al. Intermetallic compounds of Al and transitions metals: Effect of electromigration in 1-2-μm-wide lines , 1978 .
[2] S. Asai,et al. Analytical models of threshold voltage and breakdown voltage of short-channel MOSFETs derived from two-dimensional analysis , 1979, IEEE Journal of Solid-State Circuits.
[3] J. Brews. Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET , 1979, IEEE Transactions on Electron Devices.
[4] R.R. Troutman,et al. VLSI limitations from drain-induced barrier lowering , 1979, IEEE Transactions on Electron Devices.
[5] B. Eitan,et al. Surface conduction in short-channel MOS devices as a limitation to VLSI scaling , 1982, IEEE Transactions on Electron Devices.
[6] G. Baccarani,et al. IIA-1 generalized scaling theory and its application to a 1/4 micron mosfet design , 1982, IEEE Transactions on Electron Devices.
[7] K. N. Ratnakumar,et al. Short-channel MOST threshold voltage model , 1982 .
[8] J.D. Meindl. Theoretical, practical and analogical limits in ULSI , 1983, 1983 International Electron Devices Meeting.
[9] Hsing-Hai Chen,et al. AN ANALYTIC AND ACCURATE MODEL FOR THE THRESHOLD VOLTAGE OF SHORT CHANNEL MOSFETS IN VLSI , 1984 .
[10] G. Baccarani,et al. Generalized scaling theory and its application to a ¼ micrometer MOSFET design , 1984, IEEE Transactions on Electron Devices.
[11] B. Hoefflinger,et al. A parametric short-channel MOS transistor model for subthreshold and strong inversion current , 1984, IEEE Transactions on Electron Devices.
[12] Susumu Muramoto,et al. Gate Oxide Thinning Limit Influenced by Gate Materials , 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.
[13] Chenming Hu,et al. Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.
[14] J. McPherson,et al. Acceleration Factors for Thin Gate Oxide Stressing , 1985, 23rd International Reliability Physics Symposium.
[15] James D. Meindl,et al. Performance limits of CMOS ULSI , 1985 .
[16] R.H. Dennard,et al. A fully scaled submicrometer NMOS technology using direct-write E-beam lithography , 1985, IEEE Transactions on Electron Devices.
[17] J.M. Pimbley. Dual-level transmission line model for current flow in metal-semiconductor contacts , 1986, IEEE Transactions on Electron Devices.
[18] A.R. Boothroyd,et al. A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped substrates , 1986, IEEE Electron Device Letters.
[19] Pole-Shang Lin,et al. A new approach to analytically solving the two-dimensional Poisson's equation and its application in short-channel MOSFET modeling , 1987 .
[20] E. Cumberbatch,et al. Analytical treatment of MOSFET source—Drain resistance , 1987, IEEE Transactions on Electron Devices.