Dual-Band 802.11ax Transceiver Design With 1024-QAM and 160-MHz CBW Support

A $2\times 2\,\,802.11$ ax transceiver design is presented to support dual-band simultaneous operation (DBS) and 1024-QAM modulation. The proposed architecture features linearity enhancement for uplink orthogonal frequency division multiple access (OFDMA) and wideband transmission. With integrated low-phase noise clock generation and phase locked loop (PLL), best-in-class receiving sensitivity and lowest transmission EVM floor are demonstrated through measurements. With 20-MHz (HE20) receiving, −96.5/−66 dBm sensitivity level is measured for MSC0/11, respectively. The output power reaches 18 dBm with −35-dB EVM for 80 MHz 1024-QAM (HE80 MCS11) transmission at 5-GHz band. Narrowband OFDMA signals can be transmitted at full power capacity, and 160-MHz channel bandwidth (CBW) can also be supported without digital predistortion (DPD). The fully integrated transceiver occupies 10.5-mm2 silicon area in 22-nm CMOS.

[1]  Yufei Wang,et al.  A Dual-Band 2×2 802.11ax Transceiver Supporting 160MHz CBW and 1024-QAM , 2022, 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[2]  Jing-Hong Conan Zhan,et al.  10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and −43dB EVM Floor in 55nm CMOS , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[3]  Halil Volkan Hünerli,et al.  Improvement of AM–PM in a 33-GHz CMOS SOI Power Amplifier Using pMOS Neutralization , 2019, IEEE Microwave and Wireless Components Letters.

[4]  Y. Fujimura,et al.  An 802.11ax 4 $\times$ 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer , 2018, IEEE Journal of Solid-State Circuits.

[5]  Qing Liu,et al.  A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[6]  Jing-Hong Conan Zhan,et al.  A 2×2 802.11ac WiFi transceiver supporting per channel 160MHz operation in 28nm CMOS , 2017, 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[7]  Dae Hyun Kwon,et al.  13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[8]  B. Miller,et al.  A multiple modulator fractional divider , 1990, 44th Annual Symposium on Frequency Control.