A Continuous-Time MASH 1-1-1 Delta–Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS
暂无分享,去创建一个
[1] W. Snelgrove,et al. Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .
[2] Ping Chen,et al. A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).
[3] E. Sánchez-Sinencio,et al. A Continuous-Time Modulator With 88-dB Dynamic Range and 1 . 1-MHz Signal Bandwidth , 2001 .
[4] Jose Silva-Martinez,et al. A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors , 2003, IEEE J. Solid State Circuits.
[5] Shanthi Pavan,et al. A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback , 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).
[6] Michael P. Flynn,et al. A 5GS/s 156MHz BW 70dB DR continuous-time sigma-delta modulator with time-interleaved reference data-weighted averaging , 2017, 2017 Symposium on VLSI Circuits.
[7] William Yang,et al. A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.
[8] Pavan Kumar Hanumolu,et al. A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).
[9] Patrick Satarzadeh,et al. A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.
[10] John G. Kauffman,et al. A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW , 2014, IEEE Journal of Solid-State Circuits.
[11] M. Bolatkale,et al. A 4 GHz Continuous-Time $\Delta\Sigma$ ADC With 70 dB DR and $-$74 dBFS THD in 125 MHz BW , 2011, IEEE Journal of Solid-State Circuits.
[12] O. Oliaei,et al. Sigma-delta modulator with spectrally shaped feedback , 2003, IEEE Trans. Circuits Syst. II Express Briefs.
[13] Stacy Ho,et al. A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.
[14] Bruce A. Wooley,et al. A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator , 2008, VLSIC 2008.
[15] E. Sanchez-Sinencio,et al. A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth , 2004, IEEE Journal of Solid-State Circuits.
[16] Ping Chen,et al. A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[17] Samuel Palermo,et al. A 75-MHz Continuous-Time Sigma–Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage , 2017, IEEE Journal of Solid-State Circuits.
[18] Maurits Ortmanns,et al. On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma–Delta Modulators , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[19] L.J. Breems,et al. A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[20] Sheng-Jui Huang,et al. 28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[21] P. Fontaine,et al. A low-noise low-voltage CT /spl Delta//spl Sigma/ modulator with digital compensation of excess loop delay , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[22] Sunsik Woo,et al. A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[23] L.J. Breems,et al. A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth , 2004, IEEE Journal of Solid-State Circuits.
[24] Jose Silva-Martinez,et al. A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS , 2017, IEEE Journal of Solid-State Circuits.
[25] J. H. Winters,et al. Adaptive nonlinear cancellation for high-speed fiber-optic systems , 1992 .
[26] Jose Silva-Martinez,et al. Design Techniques to Improve Blocker Tolerance of Continuous-Time $\Delta\Sigma$ ADCs , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[27] Koichi Hamashita,et al. LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators , 2010, IEEE Journal of Solid-State Circuits.
[28] Hae-Seung Lee,et al. A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.
[29] Shanthi Pavan,et al. Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs , 2012, IEEE Journal of Solid-State Circuits.
[30] B. M. Putter,et al. /spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).