A Flexible Frame-Oriented Host-FPGA Communication Framework for Software Defined Wireless Network

FPGA becomes more and more attractive as accelerator platform. Many FPGA accelerators use frame oriented transmission. As there is no standard frame-oriented Host-FPGA communication framework, FPGA accelerator developers have to write significant amount of code on both FPGA side and Host side. In this paper, we present a frame-oriented high-performance Host-FPGA PCIe / USB communication framework EPEE 3.0, implements the communication library using Xilinx Kintex-7 with PCIe Gen2 X8 and USB 3.0. Simulation shows that EPEE 3.0 achieves a high throughput and can be easily used by FPGA developers.

[1]  Jason Cong,et al.  GRT: A Reconfigurable SDR Platform with High Performance and Usability , 2014, CARN.

[2]  Jason Cong,et al.  An efficient and flexible host-FPGA PCIe communication library , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

[3]  Ken Eguro,et al.  SIRC: An Extensible Reconfigurable Computing Communication API , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

[4]  Dirk Koch,et al.  JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[5]  Andreas Koch,et al.  ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators , 2016, CARN.

[6]  Kenji Kise,et al.  A Challenge of Portable and High-Speed FPGA Accelerator , 2015, ARC.