Energy efficient, noise immune 4×4 Vedic multiplier using semi-domino logic style

In this paper, implementation of an energy-efficient, low power, noise immune 4×4 Vedic Multiplier is proposed. The adder circuit used as building block in the multiplier unit is designed using semi-domino logic. The proposed multiplier unit has its benefits in terms of power consumption, delay, Energy-Delay-Product and UNG. This circuit exhibits a lower EDP of 2.88 Tena Micro to 27.97 Tena Micro, when compared with conventional and PTL logic circuits and hence, is the fastest. The simulation is done using Cadence Virtuoso in 90nm technology at 110° c temperature using 0.9 V supply voltage.