VLSI architectures for CFAR detectors based on order statistics
暂无分享,去创建一个
[1] M. Weiss,et al. Analysis of Some Modified Cell-Averaging CFAR Processors in Multiple-Target Situations , 1982, IEEE Transactions on Aerospace and Electronic Systems.
[2] S. Kung,et al. VLSI Array processors , 1985, IEEE ASSP Magazine.
[3] Saleem A. Kassam,et al. Analysis of CFAR processors in homogeneous background , 1988 .
[4] V. Hansen,et al. Detectability Loss Due to "Greatest Of" Selection in a Cell-Averaging CFAR , 1980, IEEE Transactions on Aerospace and Electronic Systems.
[5] H. T. Kung. Why systolic architectures? , 1982, Computer.
[6] G. Trunk. Range Resolution of Targets Using Automatic Detectors , 1978, IEEE Transactions on Aerospace and Electronic Systems.
[7] Hermann Rohling,et al. Radar CFAR Thresholding in Clutter and Multiple Target Situations , 1983, IEEE Transactions on Aerospace and Electronic Systems.
[8] J. A. Ritcey,et al. Detection performance and systolic architectures for OS-CFAR detectors , 1990, IEEE International Conference on Radar.
[9] Jenq-Neng Hwang,et al. Systolic architectures for radar CFAR detectors , 1991, IEEE Trans. Signal Process..