Modeling, design, and implementation of a priority buffer for embedded systems

The paper describes a model, architecture, and functionality of a priority buffer, which receives an arbitrary sequence of instructions and outputs a new sequence ordered in accordance with the priorities of the instructions that have already been received. Any new incoming instruction changes the output sequence because it has to be accommodated in the buffer on the basis of its priority. It is shown that the desired functionality of the buffer can be described efficiently by the proposed parallel hierarchical algorithms involving recursion. The algorithms have been modeled in general-purpose software and implemented in hardware (in a commercially available FPGA). The results of experiments have shown that the buffer operates in strong conformity with the requirements and specification. The required memory is allocated and deallocated dynamically. The proposed buffer architecture is easily scalable, which enables a buffer of any size to be provided.