Full-chip, three-dimensional shapes-based RLC extraction

In this paper, we report the development of a full-chip, three-dimensional, shapes-based, resistence-inductance-capacitance extraction tool, which was developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate crosstalk analysis. The tool exploits high-capacity scan-band techniques and disk caching. Accuracy is validated by comparison with full-wave finite-element field solvers.

[1]  Kenneth L. Shepard,et al.  Return-limited inductances: a practical approach to on-chip inductance extraction , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[2]  Xavier Aragones,et al.  Experimental comparison of substrate noise coupling using different wafer types , 1999 .

[3]  Jinsong Zhao,et al.  Green function via moment matching for rapid and accurate substrate parasitics evaluation , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[4]  Sorin P. Voinigescu,et al.  Circuits and technologies for highly integrated optical networking ICs at 10 Gb/s to 40 Gb/s , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[5]  B. Krauter,et al.  Including inductive effects in interconnect timing analysis , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[6]  Kuang-Wei Chiang.  Resistance Extraction and Resistance Calculation in GOALIE2 , 1989, 26th ACM/IEEE Design Automation Conference.

[7]  Lawrence T. Pileggi,et al.  Modeling magnetic coupling for on-chip interconnect , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[8]  Kenneth L. Shepard,et al.  Global Harmony: coupled noise analysis for full-chip RC interconnect networks , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[9]  Frederick Warren Grover,et al.  Inductance Calculations: Working Formulas and Tables , 1981 .

[10]  K.A. Jenkins,et al.  A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[11]  Ali M. Niknejad,et al.  Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Roger F. Harrington,et al.  Field computation by moment methods , 1968 .

[13]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Kenneth L. Shepard,et al.  Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors , 1997, IBM J. Res. Dev..

[15]  Sung-Mo Kang,et al.  Substrate modeling and lumped substrate resistance extraction for CMOS ESD/latchup circuit simulation , 1999, DAC '99.

[16]  Sharad Mehrotra,et al.  Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[17]  Gregory A. Northrop,et al.  Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors , 1999, IBM Journal of Research and Development.

[18]  J. N. Lyness.  Some Quadrature Rules for Finite Trigonometric and Related Integrals , 1987 .

[19]  Albert E. Ruehli,et al.  Retarded models for PC board interconnects-or how the speed of light affects your SPICE circuit simulation , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[20]  A. E. Ruehli,et al.  Inductance of Nonstraight Conductors Close to Ground Return Plane (Short Papers) , 1975 .

[21]  D. P. Neikirk,et al.  Compact equivalent circuit model for the skin effect , 1996, 1996 IEEE MTT-S International Microwave Symposium Digest.

[22]  E. Friedman,et al.  Figures of merit to characterize the importance of on-chip inductance , 1998, DAC.

[23]  Rajendran Panda,et al.  On-chip inductance modeling and analysis , 2000, Proceedings 37th Design Automation Conference.

[24]  A. Niknejad,et al.  Analysis , Design , and Optimization of Spiral Inductors and Transformers for Si RF IC ’ s , 1998 .

[25]  Keith A. Jenkins,et al.  Integrated RF and microwave components in BiCMOS technology , 1996 .

[26]  Chi-Yuan Lo,et al.  Time efficient VLSI artwork analysis algorithms in GOALIE2 , 1988, DAC '88.

[27]  David E. Long,et al.  Efficient thee-dimensional extraction based on static and full-wave layered Green's functions , 1998, DAC.

[28]  A. Ruehli.  Equivalent Circuit Models for Three-Dimensional Multiconductor Systems , 1974 .

[29]  Mattan Kamon,et al.  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.

[30]  J. Briaire,et al.  Principles of substrate crosstalk generation in CMOS circuits , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  David Blaauw,et al.  Inductance 101: analysis and design issues , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[32]  C. Yue,et al.  On-chip Spiral Inductors With Patterned Ground Shields For Si-based RF IC's , 1997, Symposium 1997 on VLSI Circuits.

[33]  S. Wong,et al.  Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design , 2001, IEEE J. Solid State Circuits.

[34]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1996 .

[35]  Chandramouli V. Kashyap,et al.  A realizable driving point model for on-chip interconnect with inductance , 2000, Proceedings 37th Design Automation Conference.

[36]  Joseph D. Kanapka.  Fast methods for extraction and sparsification of substrate coupling , 2000, Proceedings 37th Design Automation Conference.

[37]  George Papadopoulos,et al.  Full-wave PEEC time-domain method for the modeling of on-chipinterconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  J. Colvin,et al.  Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology , 1999 .

[39]  Jacob K. White,et al.  Simulation and modeling of the effect of substrate conductivity on coupling inductance , 1995, Proceedings of International Electron Devices Meeting.

[40]  Mattan Kamon,et al.  FASTHENRY: a multipole-accelerated 3-D inductance extraction program , 1994 .

[41]  Kari Halonen,et al.  Proceedings of the Custom Integrated Circuits Conference CICC'06 , 2006 .

[42]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[43]  Kapur,et al.  IES/sup 3/: a fast integral equation solver for efficient 3-dimensional extraction , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[44]  Hao Ji,et al.  How to efficiently capture on-chip inductance effects: introducing a new circuit element K , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[45]  Ali Hajimiri,et al.  Silicon-based distributed voltage-controlled oscillators , 2001, IEEE J. Solid State Circuits.

[46]  Ali M. Niknejad,et al.  Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs , 1998, IEEE J. Solid State Circuits.

[47]  S.-F.S. Chu,et al.  Driving CMOS into the wireless communications arena with technology scaling , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[48]  Byron L. Krauter,et al.  Generating sparse partial inductance matrices with guaranteed stability , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[49]  Shen Lin,et al.  Quick on-chip self- and mutual-inductance screen , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

[50]  W. R. Eisenstadt,et al.  S-parameter-based IC interconnect transmission line characterization , 1992 .

[51]  A. E. Ruehii.  Inductance Calculations in a Complex Integrated Circuit Environment , 2002 .

[52]  Kenneth L. Shepard,et al.  Full-chip, three-dimensional, shapes-based RLC extraction , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[53]  C. Paul,et al.  Inductance calculations using partial inductances and macromodels , 1995, Proceedings of International Symposium on Electromagnetic Compatibility.