A new full adder design for tree structured arithmetic circuits

A new low power and high speed full adder is designed which targets at tree structured applications. By employing complementary signal at input, buffer inverter at output, a new transmission gate based full adder is proposed. This new adder uses 20 transistors to achieve high driving ability and low power consumption. Simulation in Semiconductor Manufacturing International Corporation 0.18-um CMOS process indicates that the new adder outperforms the four existing adders in terms of power delay product. The design has a full voltage swing, making it suitable for technology scaling. The adder can be used for high-performance circuits such as high speed and low power multipliers.

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