论文信息 - A modified discrete Fourier-cosine transform algorithm and its VLSI implementation

A modified discrete Fourier-cosine transform algorithm and its VLSI implementation

Abstract A modified discrete Fourier-cosine transform (DFCT) algorithm and its VLSI implementation on a high speed VLSI chip are presented. The proposed DFCT algorithm achieves a considerably higher throughput rate when compared to other implementations by exploiting the inherent parallelism of the new flowgraph, proposed for the DFCT algorithm, to the full. DFCTs of greater length and two dimensional DFCTs can be performed by a set of such chips, at board level. 1.2 μm DLM CMOS technology was used for the implementation of the chip and the chip die size is 112.54 mm 2 . The throughput rate for the DFCT is 750 Mbitss 1 .

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