Controllable Inverter DelayandSuppressing VthFluctuation Technology inSilicon onThinBOX Featuring DualBack-Gate BiasArchitecture

A cross-sectional viewandprocess flowoftheSOTBare showninFigs. 1and2.Advantages ofthis structure arealso summarized in thefigure caption. A simplified hybrid SOTB LSTPapplication hasbeensuccessfully developed. Inthe andBulkCMOS technology tointegrate withperipheral SOTB device, short-channel effect immunity withoutdevices suchasI/O transistors wasdescribed elsewhere [2]. channel doping andback-gate biasthreshold voltage (Vh) Thehybrid structure canbeachieved byremoving the control aredemonstrated. GIDLisreduced withavoidingSOI/BOXlayers intheback-gate contact andbulkactive drive current andinverter delay degradation minimumby D optimizing offset source/drain extension togate overlap. We egin. Dueto the control ofthegateandsidewall havealsoproposed theSOTBdevice design enabling the betig which prevtednth re.ce and pre-clean controllable inverter delay andlowVeh fluctuation forLogic beee a l nlresistance (RsdF 190Q3m) was andSRAM memorycell transistors. Inverter delay canbe oine 4 nm-gat ig 3). improved from19.3to10.5psbyapplying theforward Figure4ss Theorinthwndow forsRAM back-gate bias. Furthermore, Vch fluctuation canbereducedmemor ce [ T h o vertixes show about~~~~~~~ 160 byaplyngte evre ac-atba. A theVth fortheNMOS andPMOS devices. Thesolid lines 6-transitor6 SRAM memoryi cellnof the OTesute by andthedashedlines showtheoperational limits defined by 6-transistor SRAM memorycell oftheSOTBstructure by th.Nsai os magn redn magn an wrtn adding areverse backbias control hasshowntodramatically thSN (sainoemrg:radgmri)adwiig adding areesebckbascntohsshwtrmargin. Theshaded region istheoperational window ofVth. improve SRAMmemorycell stability.Toimprove this operational window, itisnecessary to