Arco: A cost-effective and flexible hardware maze router

Abstract The ARCO architecture implements a cost-based version of Lee's routing algorithm. It supports two-layer routing and can be realized with the use of commercial memory chips and programmable logic devices. The architecture exploits the parallelism of the expansion and reset phases of Lee's algorithm with the use of two three-stage pipelines and a special organization of the memory which stores the board description. The algorithm retrace phase is implemented in software on the host computer. A speed-up factor over 27 in relation to an IBM-PC/486 running at 33 MHz has been achieved with an initial prototype of an accelerator based on the ARCO architecture in the routing of a two-layer printed circuit board.

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