Tutorial on VLSI Partitioning

The tutorial introduces the partitioning with applications to VLSI circuit designs. The problem formulations include two-way, multiway, and multi-level partitioning, partitioning with replication, and performance driven partitioning. We depict the models of multiple pin nets for the partitioning processes. To derive the optimum solutions, we describe the branch and bound method and the dynamic programming method for a special case of circuits. We also explain several heuristics including the group migration algorithms, network flow approaches, programming methods, Lagrange multiplier methods, and clustering methods. We conclude the tutorial with research directions.

[1]  Béla Bollobás,et al.  Random Graphs , 1985 .

[2]  A. Richard Newton,et al.  Adaptive methods for netlist partitioning , 1997, ICCAD 1997.

[3]  Ernst G. Ulrich,et al.  Clustering and linear placement , 1972, DAC '72.

[4]  Chung-Kuan Cheng,et al.  Ancestor tree for arbitrary multi-terminal cut functions , 1990, IPCO.

[5]  Chung-Kuan Cheng,et al.  A network flow approach for hierarchical tree partitioning , 1997, DAC.

[6]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[7]  Chung-Kuan Cheng,et al.  Linear placement algorithms and applications to VLSI design , 1987, Networks.

[8]  Chung-Kuan Cheng,et al.  Performance-Driven Partitioning Using a Replication Graph Approach , 1995, 32nd Design Automation Conference.

[9]  Frank Thomson Leighton,et al.  Graph bisection algorithms with good average case behavior , 1984, Comb..

[10]  Roy L. Russo,et al.  On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.

[11]  Dennis J.-H. Huang,et al.  Multilevel Circuit Partitioning , 1997, Proceedings of the 34th Design Automation Conference.

[12]  Chung-Kuan Cheng,et al.  Ratio cut partitioning for hierarchical designs , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Chung-Kuan Cheng,et al.  The optimal partitioning of networks , 1992, Networks.

[14]  Martine D. F. Schlag,et al.  Hybrid spectral/iterative partitioning , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[15]  Chung-Kuan Cheng,et al.  Data Flow Partitioning for Clock Period and Latency Minimization , 1994, 31st Design Automation Conference.

[16]  Chung-Kuan Cheng,et al.  Network partitioning into tree hierarchies , 1996, DAC '96.

[17]  Melvin A. Breuer,et al.  Design automation of digital systems , 1972 .

[18]  Godwin C. Ovuworie,et al.  Mathematical Programming: Structures and Algorithms , 1979 .

[19]  Martine D. F. Schlag,et al.  Hybrid spectral/iterative partitioning , 1997, ICCAD 1997.

[20]  Chung-Kuan Cheng,et al.  Multiple-level partitioning: an application to the very large-scale hardware simulator , 1991 .

[21]  S. Dutt,et al.  A probability-based approach to VLSI circuit partitioning , 1996, 33rd Design Automation Conference Proceedings, 1996.

[22]  I. Adler,et al.  On the partitioning of graphs and hypergraphs , 1987 .

[23]  Chingwei Yeh,et al.  Circuit clustering using a stochastic flow injection method , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  J.A.G. Jess,et al.  Two-dimensional datapath regularity extraction , 1996 .

[25]  Andrew B. Kahng,et al.  Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  D. Adolphson.  Optimal linear-ordering. , 1973 .

[27]  Majid Sarrafzadeh,et al.  Evaluation and optimization of replication algorithms for logic bipartitioning , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Chung-Kuan Cheng,et al.  Local ratio cut and set covering partitioning for huge logic emulation systems , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Cecilia R. Aragon,et al.  Optimization by Simulated Annealing: An Experimental Evaluation; Part I, Graph Partitioning , 1989, Oper. Res..

[30]  Laura A. Sanchis,et al.  Multiple-Way Network Partitioning , 1989, IEEE Trans. Computers.

[31]  Sao-Jie Chen,et al.  A stable partitioning algorithm for VLSI circuits , 1996, Proceedings of Custom Integrated Circuits Conference.

[32]  Ernest S. Kuh,et al.  Quadratic Boolean Programming for Performance-Driven System Partitioning , 1993, 30th ACM/IEEE Design Automation Conference.

[33]  J. Blanks,et al.  Partitioning by Probability Condensation , 1989, 26th ACM/IEEE Design Automation Conference.

[34]  Andrew B. Kahng,et al.  Partitioning with terminals: a “new” problem and new benchmarks , 1999, ISPD '99.

[35]  Chung-Kuan Cheng,et al.  An improved two-way partitioning algorithm with stable performance [VLSI] , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[37]  Chung-Kuan Cheng,et al.  Finite state machine decomposition for I/O minimization , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[38]  Hans Jürgen Prömel,et al.  Finding clusters in VLSI circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[39]  D. F. Wong,et al.  Efficient network flow based min-cut balanced partitioning , 1994, ICCAD 1994.

[40]  Chung-Kuan Cheng,et al.  A gradient method on the initial partition of Fiduccia-Mattheyses algorithm , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[41]  Chung-Kuan Cheng,et al.  An efficient multi-level placement technique using hierarchical partitioning , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[42]  Hyunchul Shin,et al.  A simple yet effective technique for partitioning , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[43]  Charles J. Alpert,et al.  The ISPD98 circuit benchmark suite , 1998, ISPD '98.

[44]  Brian W. Kernighan,et al.  A proper model for the partitioning of electrical circuits , 1972, DAC '72.

[45]  Naveed A. Sherwani,et al.  Algorithms for VLSI Physical Design Automation , 1999, Springer US.

[46]  Richard M. Karp,et al.  A characterization of the minimum cycle mean in a digraph , 1978, Discret. Math..

[47]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[48]  Martin D. F. Wong,et al.  Edge-map: Optimal Performance Driven Technology Mapping for Iterative Lut Based Fpga Designs , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[49]  Rajeev Motwani,et al.  Randomized Algorithms , 1995, SIGA.

[50]  Chung-Kuan Cheng,et al.  New spectral linear placement and clustering approach , 1996, DAC '96.

[51]  Charles J. Alpert,et al.  Spectral Partitioning: The More Eigenvectors, The Better , 1995, 32nd Design Automation Conference.

[52]  Jan-Ming Ho,et al.  Efficient bipartitioning algorithm for size-constrained circuits , 1998 .

[53]  Michael C. McFarland,et al.  Computer-Aided Partitioning of Behavioral Hardware Descriptions , 1983, 20th Design Automation Conference Proceedings.

[54]  Frank Thomson Leighton,et al.  An approximate max-flow min-cut theorem for uniform multicommodity flow problems with applications to approximation algorithms , 1988, [Proceedings 1988] 29th Annual Symposium on Foundations of Computer Science.

[55]  Kenneth M. Hall.  An r-Dimensional Quadratic Placement Algorithm , 1970 .

[56]  Chung-Kuan Cheng,et al.  A replication cut for two-way partitioning , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[57]  S.,et al.  An Efficient Heuristic Procedure for Partitioning Graphs , 2022 .

[58]  Howard R. Charney,et al.  Efficient partitioning of components , 1968, DAC.

[59]  A. J. Stone,et al.  Logic partitioning , 1966, DAC.

[60]  A. Richard Newton,et al.  A cell-replicating approach to minicut-based circuit partitioning , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[61]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.

[62]  Ernest S. Kuh,et al.  Performance-driven system partitioning on multi-chip modules , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[63]  Gabriele Saucier,et al.  A hierarchy-driven FPGA partitioning method , 1997, DAC.

[64]  Martine D. F. Schlag,et al.  Spectral K-way ratio-cut partitioning and clustering , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[65]  Youssef Saab,et al.  An Evolution-Based Approach to Partitioning ASIC Systems , 1989, 26th ACM/IEEE Design Automation Conference.

[66]  Farhad Shahrokhi,et al.  The maximum concurrent flow problem , 1990, JACM.

[67]  Sung-Woo Hur,et al.  Relaxation and clustering in a local search framework: application to linear placement , 1999, DAC '99.

[68]  Youssef Saab,et al.  A Fast and Robust Network Bisection Algorithm , 1995, IEEE Trans. Computers.

[69]  Chung-Kuan Cheng,et al.  BDD-based logic partitioning for sequential circuits , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[70]  Abbas El Gamal,et al.  Optimal replication for min-cut partitioning , 1992, ICCAD.

[71]  Chingwei Yeh,et al.  A general purpose multiple way partitioning algorithm , 1991, 28th ACM/IEEE Design Automation Conference.

[72]  A. Hoffman,et al.  Lower bounds for the partitioning of graphs , 1973 .

[73]  Roy L. Russo,et al.  A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs , 1971, IEEE Transactions on Computers.

[74]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: applications in VLSI domain , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[75]  Frank Thomson Leighton,et al.  Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms , 1989, 26th ACM/IEEE Design Automation Conference.

[76]  Achim G. Hoffmann.  The dynamic locking heuristic-a new graph partitioning algorithm , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[77]  Fillia Makedon,et al.  Fast approximation algorithms for multicommodity flow problems , 1991, STOC '91.

[78]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.

[79]  Chung-Kuan Cheng,et al.  Module Placement Based on Resistive Network Optimization , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[80]  Laura A. Sanchis,et al.  Multiple-Way Network Partitioning with Different Cost Functions , 1993, IEEE Trans. Computers.

[81]  Balakrishnan Krishnamurthy,et al.  An Improved Min-Cut Algonthm for Partitioning VLSI Networks , 1984, IEEE Transactions on Computers.

[82]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[83]  Andrew B. Kahng,et al.  New spectral methods for ratio cut partitioning and clustering , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[84]  Shantanu Dutt,et al.  VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, Proceedings of International Conference on Computer Aided Design.

[85]  R. Burkard,et al.  A heuristic for quadratic Boolean programs with applications to quadratic assignment problems , 1983 .

[86]  Jaeseok Kim,et al.  An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation. , 1993, 30th ACM/IEEE Design Automation Conference.

[87]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[88]  David S. Johnson,et al.  Computers and Inrracrobiliry: A Guide ro the Theory of NP-Completeness , 1979 .

[89]  Ravi B. Boppana,et al.  Eigenvalues and graph bisection: An average-case analysis , 1987, 28th Annual Symposium on Foundations of Computer Science (sfcs 1987).

[90]  Abhijit Chatterjee,et al.  A new simultaneous circuit partitioning and chip placement approach based on simulated annealing , 1991, DAC '90.

[91]  Chung-Kuan Cheng,et al.  Linear decomposition algorithm for VLSI design applications , 1995, ICCAD.

[92]  Konrad Doll,et al.  Partitioning Very Large Circuits Using Analytical Placement Techniques , 1994, 31st Design Automation Conference.

[93]  Carl Sechen,et al.  An improved objective function for mincut circuit partitioning , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[94]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[95]  Chingwei Yeh,et al.  Optimization by iterative improvement: an experimental evaluation on two-way partitioning , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[96]  Andrew B. Kahng,et al.  A general framework for vertex orderings with applications to circuit clustering , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[97]  J. Cong,et al.  Multi-way VLSI Circuit Partitioning Based On Dual Net Representation , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[98]  Keshab K. Parhi,et al.  Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding , 1991, IEEE Trans. Computers.

[99]  Carl Sechen,et al.  A timing driven N-way chip and multi-chip partitioner , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[100]  Chung-Kuan Cheng,et al.  Circuit partitioning for pipelined pseudo-exhaustive testing using simulated annealing , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[101]  Thomas Lengauer,et al.  Linear arrangement problems on recursively partitioned graphs , 1988, ZOR Methods Model. Oper. Res..

[102]  Jason Cong,et al.  Large scale circuit partitioning with loose/stable net removal and signal flow based clustering , 1997, ICCAD 1997.

[103]  David S. Johnson,et al.  Computers and In stractability: A Guide to the Theory of NP-Completeness. W. H Freeman, San Fran , 1979 .

[104]  Chingwei Yeh.  On the acceleration of flow-oriented circuit clustering , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..