A new fully integrated CMOS phase-locked loop with low jitter and fast lock time

In this paper we describe a novel PLL circuit design. The proposed topology is based on two loops: the conventional fine loop and a new coarse loop. The fine tuning loop which includes a phase-frequency detector, a charge pump and a differential voltage controlled oscillator (unity feedback PLL) is rather slow. However the coarse tuning loop reacts faster and accelerates convergence. It also ensures a better stability, a shorter locking time, and as a result, a low jitter is obtained, as well as a lower sensitivity to power supply variations.

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