NBTI in (Si)Ge Channel Devices

This chapter focuses on the negative bias temperature instability (NBTI) of the novel Ge-based high-mobility channel pMOS technology, with Si passivation scheme and SiO2/HfO2 dielectric stack. We observe that this technology offers a remarkable reliability improvement. In particular, a significantly reduced NBTI is obtained by optimizing the gate stack with a high Ge fraction in the channel, a sufficiently thick channel quantum well, and a Si passivation layer of reduced thickness. By means of such optimization, sufficiently reliable ultrathin EOT SiGe pMOSFETs with a 10-year lifetime at operating conditions are demonstrated in both gate-first and gate-last process flows. Furthermore, the reliability improvement is observed to be process independent and architecture independent, proving to be an intrinsic property of the studied MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack.

[1]  A. Mercha,et al.  High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD , 2010, 2010 International Electron Devices Meeting.

[2]  S. Narasimha,et al.  A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications , 2011, 2011 International Electron Devices Meeting.

[3]  Zhang Yue,et al.  Negative Bias Temperature Instability "Recovery" under Negative Stress Voltage with Different Oxide Thicknesses ∗ , 2011 .

[4]  E. Cartier,et al.  Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling , 2011, 2011 International Electron Devices Meeting.

[5]  John Robertson,et al.  Passivation of oxygen vacancy states and suppression of Fermi pinning in HfO2 by La addition , 2009 .

[6]  B. Kaczer,et al.  Improvements of NBTI reliability in SiGe p-FETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[7]  Anabela Veloso,et al.  Significant reduction of Positive Bias Temperature Instability in high-k/metal-gate nFETs by incorporation of rare earth metals , 2009 .

[8]  A. Shluger,et al.  Vacancy and interstitial defects in hafnia , 2002 .

[9]  M. Denais,et al.  NBTI degradation: From physical mechanisms to modelling , 2006, Microelectron. Reliab..

[10]  G. Groeseneken,et al.  From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[11]  K. J. Kuhn,et al.  Considerations for Ultimate CMOS Scaling , 2012, IEEE Transactions on Electron Devices.

[12]  Y. Yeo,et al.  Fabrication and Negative Bias Temperature Instability (NBTI) Study on Ge0.97Sn0.03 P-MOSFETs with Si2H6 Passivation and HfO2 High-k and TaN Metal Gate , 2013 .

[13]  T. Grasser,et al.  Simultaneous Extraction of Recoverable and Permanent Components Contributing to Bias-Temperature Instability , 2007, 2007 IEEE International Electron Devices Meeting.

[14]  A. Stesmans,et al.  ESR of interfaces and nanolayers in semiconductor heterostructures , 2008 .

[15]  B. Kaczer,et al.  Characterization of Individual Traps in High-κ Oxides , 2014 .

[16]  Marc Heyns,et al.  The IMEC clean : A new concept for particle and metal removal on Si surfaces , 1995 .

[17]  Jerome Mitard,et al.  Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs , 2009 .

[18]  M. Nelhiebel,et al.  The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps , 2011, IEEE Transactions on Electron Devices.

[19]  T. Ando,et al.  Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate-first process , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[20]  Andrew R. Brown,et al.  RTS amplitudes in decananometer MOSFETs: 3-D simulation study , 2003 .

[21]  R. Degraeve,et al.  Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices , 2012, IEEE Transactions on Electron Devices.

[22]  B. Kaczer,et al.  Recent advances in understanding the bias temperature instability , 2010, 2010 International Electron Devices Meeting.

[23]  T. Grasser,et al.  Time-dependent defect spectroscopy for characterization of border traps in metal-oxide-semiconductor transistors , 2010 .

[24]  Jerome Mitard,et al.  The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs , 2009 .

[25]  L. Witters,et al.  8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS , 2010, 2010 Symposium on VLSI Technology.

[26]  T. Grasser,et al.  Negative bias temperature instability: Recoverable versus permanent degradation , 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

[27]  A. Visconti,et al.  Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories , 2009, IEEE Transactions on Electron Devices.

[28]  Tibor Grasser,et al.  Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities , 2012, Microelectron. Reliab..

[29]  J. Martin-Martinez,et al.  Time-dependent variability of high-k based MOS devices: Nanoscale characterization and inclusion in circuit simulators , 2011, 2011 International Electron Devices Meeting.

[30]  Jacopo Franco,et al.  Statistical Distribution of Defect Parameters , 2014 .

[31]  G. Groeseneken,et al.  Atomistic approach to variability of bias-temperature instability in circuit simulations , 2011, 2011 International Reliability Physics Symposium.

[32]  T. Grasser,et al.  Ubiquitous relaxation in BTI stressing—New evaluation and insights , 2008, 2008 IEEE International Reliability Physics Symposium.

[33]  V. Huard,et al.  NBTI degradation: From transistor to SRAM arrays , 2008, 2008 IEEE International Reliability Physics Symposium.

[34]  Vincent Huard,et al.  From defects creation to circuit reliability - A bottom-up approach (invited) , 2011 .

[35]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[36]  R. Degraeve,et al.  6Å EOT Si0.45Ge0.55 pMOSFET with optimized reliability (VDD=1V): Meeting the NBTI lifetime target at ultra-thin EOT , 2010, 2010 International Electron Devices Meeting.

[37]  T. Grasser,et al.  Reduction of the BTI time-dependent variability in nanoscaled MOSFETs by body bias , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[38]  Liesbeth Witters,et al.  Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession , 2010 .

[39]  G. Groeseneken,et al.  A reliable approach to charge-pumping measurements in MOS transistors , 1984, IEEE Transactions on Electron Devices.

[40]  B. Kaczer,et al.  Impact of Epi-Si growth temperature on Ge-pFET performance , 2009, 2009 Proceedings of the European Solid State Device Research Conference.

[41]  Fikru Adamu-Lema,et al.  Statistical Study of Bias Temperature Instabilities by Means of 3D 'Atomistic' Simulation , 2014 .

[42]  B. Parvais,et al.  Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[43]  Liesbeth Witters,et al.  SiGe SEG Growth for Buried Channels p-MOS Devices , 2009 .

[44]  Jerome Mitard,et al.  On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si0.45Ge0.55 pMOSFETs , 2011 .