An Intelligent Multi-Port Memory

Multi-processors systems provide excellent computing ability for varied AI applications. Because processors may issue simultaneous accesses to the shared memory system, multi-port memory are widely used current multi-processor systems. This paper proposes an intelligent multi-port memory. With the help of port-priority and r/w-priority, our multi-port memory can resolve both write-write conflict and read-write conflict. When write-write conflict occurs, the port with the highest priority can execute its write operation; when read-write conflict occurs, the multi-port memory intelligently chooses read-then-write or write-then-read according to r/w-priority. Besides, direct data-switch paths between ports are implemented by utilizing the read-write conflict. We verify our design on Xilinx Virtex-E FPGA. Experiment results show that our design works well. Experiment results also show that, as the port number N increases, the cell cost increases significantly. This restricts the reasonable port number to rather small values in practice.

[1]  Wen-Ben Jone,et al.  A built-in self-testing method for embedded multiport memory arrays , 2004, IEEE Transactions on Instrumentation and Measurement.

[2]  H.J. Mattausch.  Hierarchical N-port memory architecture based on 1-port memory cells , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[3]  Mary K. Vernon,et al.  Analytic Evaluation of Shared-Memory Architectures , 2003, IEEE Trans. Parallel Distributed Syst..

[4]  Nikil D. Dutt,et al.  Library mapping for memories , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[5]  Ranga Vemuri,et al.  Global memory mapping for FPGA-based reconfigurable systems , 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

[6]  Jason Cong,et al.  Technology mapping for FPGAs with embedded memory blocks , 1998, FPGA '98.

[7]  Mary K. Vernon,et al.  Analytic evaluation of shared-memory systems with ILP processors , 1998, ISCA.

[8]  Said Hamdioui,et al.  Thorough testing of any multiport memory with linear tests , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Jason Cong,et al.  Synthesis for FPGAs with embedded memory blocks , 2000, FPGA '00.

[10]  Ranga Vemuri,et al.  Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[11]  Wen-Tsong Shiue.  Low power multiport memories exploration and design , 2001, Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555).

[12]  Steven J. E. Wilton,et al.  Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays , 1999, FPL.

[13]  Steven J. E. Wilton,et al.  Architectures and algorithms for field-programmable gate arrays with embedded memory , 1997 .