Implicit state enumeration of finite state machines using BDD's
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Robert K. Brayton | Alberto L. Sangiovanni-Vincentelli | Bill Lin | Hervé J. Touati | Hamid Savoj | R. Brayton | A. Sangiovanni-Vincentelli | H. Touati | H. Savoj | Bill Lin
[1] Edmund M. Clarke,et al. Sequential circuit verification using symbolic model checking , 1991, DAC '90.
[2] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[3] Srinivas Devadas,et al. Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[4] Albert R. Wang,et al. Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[5] Olivier Coudert,et al. Verifying Temporal Properties of Sequential Machines without Building Their State Diagrams , 1990, CAV.
[6] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.