Voltage-based electromigration immortality check for general multi-branch interconnects

As VLSI technology features are pushed to the limit with every generation and with the introduction of new materials and increased current densities to satisfy the performance demands, Electromigration (EM) is projected to be a key reliability issue for current and future VLSI technologies. Existing EM signoff mainly relies on current density-based assessment using Black's equation and Blech product. This model does not work well for multi-branch interconnect wires as the stresses developed in each wire segment is not independent of one another. In this paper, we present a novel and fast EM Immortality check for general multi-branch interconnect trees. Instead of using current density as the key parameter as in traditional methods, the new method estimates the EM-induced stress in general multi-branch interconnects based on the terminal voltages or potentials. It can be viewed as the Blech product for multi-branch interconnects for fast check of EM immortality of wires. Besides, this voltage-based EM (VBEM) assessment technique can naturally comprehend the impact of the topology of the wire structure on EM-induced stress. As a result, this new VBEM analysis method is very amenable to EM violation fixing as it brings new capabilities to the physical design stage. The VBEM stress estimation method is based on the fundamental steady-state stress equations. This approach eliminates the need for complex look-up tables for different geometries and can be implemented in CAD tools very easily as we demonstrate on real design examples. We show that its solution is consistent with the physics-based dynamic EM stress evaluations from the numerical analysis by COMSOL.

[1]  김찬홍,et al.  다중물리 해석 프로그램 : COMSOL Multiphysics , 2006 .

[2]  Jiwoo Pak,et al.  Modeling of electromigration in through-silicon-via based 3D IC , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[3]  M. Korhonen,et al.  Stress evolution due to electromigration in confined metal lines , 1993 .

[4]  Sheldon X.-D. Tan,et al.  Physics-based electromigration assessment for power grid networks , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  V. Sukharev Beyond Black’s equation: Full-chip EM/SM assessment in 3D IC stack , 2014 .

[6]  Jiwoo Pak,et al.  Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[7]  E. Demircan,et al.  Model based method for electro-migration stress determination in interconnects , 2014, 2014 IEEE International Reliability Physics Symposium.

[8]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[9]  Jiwoo Pak,et al.  Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[10]  W. Nix,et al.  Microstructure Effect on EM-Induced Degradations in Dual Inlaid Copper Interconnects , 2009, IEEE Transactions on Device and Materials Reliability.

[11]  Valeriy Sukharev,et al.  Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  I. Blech Electromigration in thin aluminum films on titanium nitride , 1976 .

[13]  Xin Zhao,et al.  Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[14]  A. S. Oates,et al.  An Electromigration Failure Distribution Model for Short-Length Conductors Incorporating Passive Sinks/Reservoirs , 2013, IEEE Transactions on Device and Materials Reliability.

[15]  Sheldon X.-D. Tan,et al.  Interconnect reliability modeling and analysis for multi-branch interconnect trees , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).